SLVSGA9A March   2022  – August 2022 TPS55289

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC Power Supply
      2. 7.3.2  EXTVCC Power Supply
      3. 7.3.3  Operation Mode Setting
      4. 7.3.4  Input Undervoltage Lockout
      5. 7.3.5  Enable and Programmable UVLO
      6. 7.3.6  Soft Start
      7. 7.3.7  Shutdown and Load Discharge
      8. 7.3.8  Switching Frequency
      9. 7.3.9  Switching Frequency Dithering
      10. 7.3.10 Inductor Current Limit
      11. 7.3.11 Internal Charge Path
      12. 7.3.12 Output Voltage Setting
      13. 7.3.13 Output Current Monitoring and Cable Voltage Droop Compensation
      14. 7.3.14 Output Current Limit
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Output Short Circuit Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Mode
      2. 7.4.2 Power Save Mode
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Target Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multiread and Multiwrite
    6. 7.6 Register Maps
      1. 7.6.1 REF Register (Address = 0h, 1h)
      2. 7.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]
      3. 7.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]
      4. 7.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]
      5. 7.6.5 CDC Register (Address = 5h) [reset = 11100000h]
      6. 7.6.6 MODE Register (Address = 6h) [reset = 00100000h]
      7. 7.6.7 STATUS Register (Address = 7h) [reset = 00000011h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 3.0 30 V
VVIN_UVLO Under voltage lockout threshold VIN rising 2.8 2.9 3.0 V
VIN falling 2.6 2.65 2.7 V
IQ Quiescent current into VIN pin IC enabled, no load, no switching. VIN = 3.0 V to 24 V, VOUT = 0.8 V, VFB = VREF + 0.1 V, RFSW = 100 kΩ, TJ up to 125°C 760 860 µA
Quiescent current into VOUT pin IC enabled, no load, no switching, VIN = 3.0 V, VOUT = 3 V to 20 V, VFB = VREF + 0.1 V, RFSW = 100 kΩ, TJ up to 125°C 760 860 µA
ISD Shutdown current into VIN pin IC disabled, VIN = 3.0 V to 14 V, TJ up to 125°C 0.8 3 µA
VCC Internal regulator output IVCC = 50 mA, VIN = 8 V, VOUT = 20 V 5.0 5.2 5.4 V
EN/UVLO
VEN_H EN logic high threshold VCC = 3.0 V to 5.5 V 1.15 V
VEN_L EN logic low threshold VCC = 3.0 V to 5.5 V 0.4 V
VEN_HYS Enable threshold hysteresis VCC = 3.0 V to 5.5 V 0.04 V
VUVLO UVLO rising threshold at the EN/UVLO pin VCC = 3.0 V to 5.5 V 1.20 1.23 1.26 V
VUVLO_HYS UVLO threshold hysteresis VCC = 3.0 V to 5.5 V 10 mV
IUVLO Sourcing current at the EN/UVLO pin VEN/UVLO = 1.3 V 4.5 5 5.5 µA
OUTPUT
VOUT Output voltage range 0.8 22 V
VOVP Output overvoltage protection threshold 22.5 23.5 24.5 V
VOVP_HYS Overvoltage protection hysteresis 1 V
IFB_LKG Leakage current at FB pin Tj up to 125°C 100 nA
IVOUT_LKG Leakage current into VOUT pin IC disabled, VOUT = 20 V, VSW2 = 0 V, TJ up to 125°C 1 20 µA
IDISCHG Output discharge current VOUT = 20 V, VCC = 5.2 V 40 100 170 mA
INTERNAL REFERENCE DAC
Resolution of reference voltage DAC 11 bits
VOUT_FULL Output voltage when VREF is set to 1.129 V VOUT_FS=03h, REF=0780h, VREF = 1.129 V 19.7 20 20.3 V
VOUT_FS=02h, REF=0780h, VREF = 1.129 V 14.78 15 15.22 V
VOUT_FS=01h, REF=0780h, VREF = 1.129 V 9.85 10 10.15 V
VOUT_FS=00h, REF=0780h, VREF = 1.129 V 4.93 5 5.07 V
VOUT_ZERO Output voltage when VREF is set to 45 mV VOUT_FS=03h, REF=0000h, VREF = 45 mV 0.74 0.8 0.86 V
VOUT_FS=02h, REF=0000h, VREF = 45 mV 0.55 0.6 0.65 V
VOUT_FS=01h, REF=0000h, VREF = 45 mV 0.36 0.4 0.44 V
VOUT_FS=00h, REF=0000h, VREF = 45 mV 0.18 0.2 0.22 V
REFERENCE VOLTAGE
VREF Reference voltage at the FB/INT pin when using external feedback External feedback with REF=0780H 1.117 1.129 1.141 V
External feedback with REF=058CH 0.837 0.846 0.855 V
External feedback with REF=0334H 0.502 0.508 0.514 V
External feedback with REF=01A4H 0.276 0.282 0.288 V
POWER SWITCH
RDS(on) Low-side MOSFET on resistance on buck side VOUT = 20 V, VCC = 5.2 V 22 mΩ
High-side MOSFET on resistance on buck side VOUT = 20 V, VCC = 5.2 V 14 mΩ
Low-side MOSFET on resistance on boost side VOUT = 20 V, VCC = 5.2 V 11 mΩ
High-side MOSFET on resistance on boost side VOUT = 20 V, VCC = 5.2 V 11 mΩ
INTERNAL CLOCK
fSW Switching frequency RFSW = 100 k 180 200 220 kHz
RFSW = 8.4 k 2000 2200 2400 kHz
tOFF_min Minimum off time Boost mode 90 145 ns
tON_min Minimum on time Buck mode 90 130 ns
VSW Voltage at the FSW pin 1 V
CURRENT LIMIT
ILIM_AVG Average inductor current limit VIN = 8 V, VOUT = 20 V, fSW = 400 kHz, FPWM 6.7 8 A
VIN = 8 V, VOUT = 20 V, fSW = 400 kHz, PFM 6.7 8 A
ILIM_PK Peak inductor current limit at boost high side VIN = 8 V, VOUT = 20 V, fSW  = 400 kHz, FPWM 13 A
VIN = 8 V, VOUT = 20 V, fSW = 400 kHz, PFM 13 A
VSNS Current loop regulation voltage between ISP and ISN pin VISN = 2 V to 21 V, IOUT_LIMIT register = 10111100b 28.5 30 31.5 mV
VISN = 2 V to 21 V, IOUT_LIMIT register = 11100100b 48 50 52 mV
CABLE VOLTAGE DROP COMPENSATION
VCDC Voltage at the CDC pin RCDC = 20 kΩ or floating, VISP – VISN = 50 mV 0.93 1 1.05 V
RCDC = 20 kΩ or floating, VISP – VISN = 2 mV 40 75 mV
VOUT_CDC VOUT increase for cable drop compensation Internal output feedback, CDC[2:0]=111, VISP – VISN = 50 mV 650 700 750 mV
Internal output feedback, CDC[2:0]=111, VISP – VISN = 2 mV 30 60 mV
Internal output feedback, CDC[2:0]=001, VISP – VISN = 50 mV 70 100 130 mV
Internal output feedback, CDC[2:0]=001, VISP – VISN = 10 mV 20 40 mV
IFB_CDC FB/INT  pin sinking current External output feedback, RCDC = 20 kΩ, VISP – VISN = 50 mV 7.23 7.5 7.87 µA
External output feedback, RCDC = 20 kΩ, VISP – VISN = 0 mV 0 0.3 µA
External output feedback, RCDC = floating, VISP – VISN = 50 mV 0 0.3 µA
ERROR AMPLIFIER
ISINK COMP pin sink current VFB = VREF + 400 mV, VCOMP = 1.1 V, VCC = 5 V 20 µA
ISOURCE COMP pin source current VFB = VREF – 400 mV, VCOMP = 1.1 V, VCC = 5 V 60 µA
VCCLPH High clamp voltage at the COMP pin 1.2 V
VCCLPL Low clamp voltage at the COMP pin 0.7 V
GEA Error amplifier transconductance 190 µA/V
SOFT START
tSS Soft-start time 2.5 3.6 5 ms
SPREAD SPECTRUM
IDITH_CHG Dithering charge current VDITH/SYNC = 1.0 V; RFSW = 49.9 kΩ; voltage rising from 0.9 V 2 µA
IDITH_DIS Dithering discharge current VDITH/SYNC = 1.0 V; RFSW = 49.9 kΩ; voltage falling from 1.1 V 2 µA
VDITH_H Dither high threshold 1.07 V
VDITH_L Dither low threshold 0.93 V
SYNCHRONOUS CLOCK
VSNYC_H Sync clock high voltage threshold 1.2 V
VSYNC_L Sync clock low voltage threshold 0.4 V
tSYNC_MIN Minimum sync clock pulse width 50 ns
HICCUP
tHICCUP Hiccup off time 76 ms
MODE  
VMODE_H MODE logic high  threshold VCC = 3.0 V to 5.5 V 1.2 V
VMODE_L MODE logic low  threshold VCC = 3.0 V to 5.5 V 0.4 V
EXTVCC
VEXTVCC_H EXTVCC logic high threshold VCC = 3.0 V to 5.5 V 1.2 V
VEXTVCC_L EXTVCC logic low threshold VCC = 3.0 V to 5.5 V 0.4 V
LOGIC INTERFACE
VI2C_IO IO voltage range for I2C 1.7 5.5 V
VI2C_H I2C input high threshold VCC = 3.0 V to 5.5 V 1.2 V
VI2C_L I2C input low threshold VCC = 3.0 V to 5.5 V 0.4 V
IFB/INT_H Leakage current into FB/INT pin when outputting high impedance VFB/INT = 5 V 100 nA
VFB/INT_L Output low voltage range of the FB/INT pin Sinking 4-mA current 0.03 0.1 V
PROTECTION
TSD Thermal shutdown threshold TJ rising 175 °C
TSD_HYS Thermal shutdown hysteresis TJ falling below TSD 20 °C