SLVSD90 December   2015 TPS563201 , TPS563208

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adaptive On-Time Control and PWM Operation
      2. 7.3.2 Pulse Skip Control (TPS563201)
      3. 7.3.3 Soft Start and Pre-Biased Soft Start
      4. 7.3.4 Current Protection
      5. 7.3.5 Undervoltage Lockout (UVLO) Protection
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Eco-mode Operation
      3. 7.4.3 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The devices are typical step-down DC-DC converters. It typically uses to convert a higher dc voltage to a lower dc voltage with a maximum available output current of 3 A. The following design procedure can be used to select component values for the TPS563201 and TPS563208. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.

8.2 Typical Application

The application schematic in Figure 19 was developed to meet the previous requirements. This circuit is available as the evaluation module (EVM). The sections provide the design procedure.

Figure 19 shows the TPS563201 and TPS563208 4.5-V to 17-V input, 1.05-V output converter schematics.

Figure 19. TPS563201 and TPS563208 1.05-V/3-A Reference Design

8.2.1 Design Requirements

Table 1 shows the design parameters for this application.

Table 1. Design Parameters

PARAMETER EXAMPLE VALUE
Input voltage range 4.5 to 17 V
Output voltage 1.05 V
Transient response, 1.5-A load step ΔVout = ±5%
Input ripple voltage 400 mV
Output ripple voltage 30 mV
Output current rating 3 A
Operating frequency 580 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.

To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more susceptible to noise and voltage errors from the VFB input current will be more noticeable.

Equation 2. TPS563201 TPS563208 Eq_02_SLVSD90.gif

8.2.2.2 Output Filter Selection

The LC filter used as the output filter has double pole at:

Equation 3. TPS563201 TPS563208 Eq_03_SLVSD90.gif

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.

Table 2. Recommended Component Values

OUTPUT VOLTAGE (V) R1 (kΩ) R2 (kΩ) L1 (µH) C8 + C9 (µF)
MIN TYP MAX
1 3.09 10.0 1.5 2.2 4.7 20 to 68
1.05 3.74 10.0 1.5 2.2 4.7 20 to 68
1.2 5.76 10.0 1.5 2.2 4.7 20 to 68
1.5 9.53 10.0 1.5 2.2 4.7 20 to 68
1.8 13.7 10.0 1.5 2.2 4.7 20 to 68
2.5 22.6 10.0 2.2 2.2 4.7 20 to 68
3.3 33.2 10.0 2.2 2.2 4.7 20 to 68
5 54.9 10.0 3.3 3.3 4.7 20 to 68
6.5 75 10.0 3.3 3.3 4.7 20 to 68

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.

Equation 4. TPS563201 TPS563208 Eq_04_SLVSD90.gif
Equation 5. TPS563201 TPS563208 Eq_05_SLVSD90.gif
Equation 6. TPS563201 TPS563208 Eq_06_SLVSD90.gif

For this design example, the calculated peak current is 3.5 A and the calculated RMS current is 3.01 A. The inductor used is a WE 74431122 with a peak current rating of 13 A and an RMS current rating of 9 A.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS563201 and TPS563208 are intended for use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7 to determine the required RMS current rating for the output capacitor.

Equation 7. TPS563201 TPS563208 Eq_07_SLVSD90.gif

For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.

8.2.2.3 Input Capacitor Selection

The TPS563201 and TPS563208 require an input decoupling capacitor and a bulk capacitor is needed depending on the application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage rating needs to be greater than the maximum input voltage.

8.2.2.4 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI recommends to use a ceramic capacitor.

8.2.3 Application Curves

TPS563201 TPS563208 D019_SLVSD90.gif
Figure 20. TPS563201 and TPS563208 Load Regulation, VIN = 5 V
TPS563201 TPS563208 D021_SLVSD90.gif
IOUT of TPS563201: 1 A
IOUT of TPS563208: 10 mA
Figure 22. TPS563201 and TPS563208 Line Regulation
TPS563201 TPS563208 TPS563201_Input_Volt_Ripple_SLVSD90.gif
800 ns/div
Figure 24. TPS563201 Input Voltage Ripple
TPS563201 TPS563208 TPS563201_Output_Volt_Ripple_0p25A_SLVSD90.gif
1 µs/div
Figure 26. TPS563201 Output Voltage Ripple, Iout = 0.25 A
TPS563201 TPS563208 TPS563208_Output_Volt_Ripple_Fig_SLVSD90.gif
800 ns/div
Figure 28. TPS563208 Output Voltage Ripple, IOUT = 0 A
TPS563201 TPS563208 TPS563201_Trans_Resp_0p75_-2p25A_SLVSD90.gif
100 µs/div
Figure 30. TPS563201 Transient Response, 0.75 to 2.25 A
TPS563201 TPS563208 TPS563201_Start_Up_VI_SLVSD90.gif
2 ms/div
Figure 32. TPS563201 Start Up Relative to VI
TPS563201 TPS563208 TPS563201_Shut_Down_VI_SLVSD90.gif
10 ms/div
Figure 34. TPS563201 Shutdown Relative to VI
TPS563201 TPS563208 D020_SLVSD90.gif
Figure 21. TPS563201 and TPS563208 Load Regulation, VIN = 12 V
TPS563201 TPS563208 D022_SLVSD90.gif
Figure 23. TPS563201 Efficiency
TPS563201 TPS563208 TPS563201_Output_Volt_Ripple_10mA_SLVSD90.gif
20 µs/div
Figure 25. TPS563201 Output Voltage Ripple, 10 mA
TPS563201 TPS563208 TPS563201_Output_Volt_Ripple_2A_SLVSD90.gif
1 µs/div
Figure 27. TPS563201 Output Voltage Ripple, Iout = 2 A
TPS563201 TPS563208 TPS563201_Trans_Resp_0p1_-1p5A_SLVSD90.gif
100 µs/div
Figure 29. TPS563201 Transient Response, 0.1 to 1.5 A
TPS563201 TPS563208 TPS563208_Trans_Resp_0p1-2A_SLVSD90.gif
100 µs/div
Figure 31. TPS563208 Transient Response 0.1 to 2 A
TPS563201 TPS563208 TPS563201_Start_Up_EN_SLVSD90.gif
400 µs/div
Figure 33. TPS563201 Start-Up Relative to EN
TPS563201 TPS563208 TPS563201_Shut_Down_EN_SLVSD90.gif
100 µs/div
Figure 35. TPS563201 Shutdown Relative to EN