SLVSAP2C December   2010  – February 2016 TPS57060-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Low Dropout Operation and Bootstrap Voltage (BOOT)
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout (UVLO)
      8. 7.3.8  Slow Start and Tracking Pin (SS/TR)
      9. 7.3.9  Overload Recovery Circuit
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection and Frequency Shift
      12. 7.3.12 Selecting the Switching Frequency
      13. 7.3.13 How to Interface to RT/CLK Pin
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Transient Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small-Signal Model for Peak Current-Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sequencing
      2. 7.4.2 Pulse Skip Eco-Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 Discontinuous Mode and Eco Mode Boundary
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN –0.3 65 V
EN(2) –0.3 5
BOOT 73
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-PH 8 V
PH DC voltage –0.6 65
200 ns –1 65
30 ns –2 65
DC voltage, TJ = –40°C –0.85 65
Voltage difference PAD to GND –200 200 mV
Source current EN 100 μA
BOOT 100 mA
VSENSE 10 μA
PH Current Limit
RT/CLK 100 μA
Sink current VIN Current Limit
COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the Enable and Adjusting Undervoltage Lockout (UVLO) section for details.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 All pins ±500
Corner pins (1, 5, 6, and 10) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN supply voltage 3.5 60 V
Output voltage for adjustable voltage 0.8 VIN V
Output current capability 0.5 A
Effective input capacitance 3 µF
Operating Ambient temperature, TA –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS57060-Q1 UNIT
DGQ (MSOP-PowerPAD) DRC (VSON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 67.4 45.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 46.7 52.1 °C/W
RθJB Junction-to-board thermal resistance 38.4 20.6 °C/W
ψJT Junction-to-top characterization parameter 1.9 0.9 °C/W
ψJB Junction-to-board characterization parameter 38.1 20.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 15.9 5.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See the Power Dissipation Estimate section for more information.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 60 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V 1.3 4 μA
EN = 0 V, 125°C, 3.5 V ≤ VIN ≤ 60 V 1.9 6.5
Operating: nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 116 136 μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.15 1.25 1.36 V
Input current Enable threshold +50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
Voltage reference 0.792 0.8 0.808 V
HIGH-SIDE MOSFET
On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 97 μMhos
Error amplifier transconductance (gM) during slow start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 26 μMhos
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±7 μA
COMP to switch current transconductance 1.9 A/V
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ = 25°C 0.6 0.94 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency using RT mode VIN = 12 V 100 2500 kHz
fSW Switching frequency VIN = 12 V, RT = 200 kΩ 450 581 720 kHz
Switching frequency using CLK mode VIN = 12 V 300 2200 kHz
Minimum CLK input pulse width 40 ns
RT/CLK high threshold VIN = 12 V 1.9 2.2 V
RT/CLK low threshold VIN = 12 V 0.45 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.0 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 112 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
PWRGDTH PWRGD switching threshold as % of the nominal VSENSE VSENSE falling (fault) 92 % of VSENSE
VSENSE rising (good) 94
VSENSE rising (fault) 109
VSENSE falling (good) 107
Hysteresis VSENSE falling and rising 2 % of VSENSE
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA 0.95 1.5 V

6.6 Typical Characteristics

TPS57060-Q1 rdson_tj_lvsa25.gif
Figure 1. On Resistance vs Junction Temperature
TPS57060-Q1 imax_tj_lvsa25.gif
Figure 3. Switch Current Limit vs Junction Temperature
TPS57060-Q1 fs_rt_clk_lvsa25.gif
Figure 5. Switching Frequency vs RT/CLK Resistance High-Frequency Range
TPS57060-Q1 ea_tj_lvsa25.gif
Figure 7. EA Transconductance During Slow Start vs Junction Temperature
TPS57060-Q1 en_tj_lvsa25.gif
Figure 9. EN Pin Voltage vs Junction Temperature
TPS57060-Q1 ic2_tj_lvsa25.gif
Figure 11. EN Pin Current vs Junction Temperature
TPS57060-Q1 ss_tr2_tj_lvsa25.gif
Figure 13. SS/TR Discharge Current vs Junction Temperature
TPS57060-Q1 icc_tj_lvsa25.gif
Figure 15. Shutdown Supply Current vs Junction Temperature
TPS57060-Q1 icc2_tj_lvsa25.gif
Figure 17. VIN Supply Current vs Junction Temperature
TPS57060-Q1 rdson2_tj_lvsa25.gif
Figure 19. PWRGD On Resistance vs Junction Temperature
TPS57060-Q1 boot_tj_lvsa25.gif
Figure 21. BOOT-PH UVLO vs Junction Temperature
TPS57060-Q1 offset_vs_lvs795.gif
Figure 23. SS/TR to VSENSE Offset vs VSENSE
TPS57060-Q1 vref_tj_lvsa25.gif
Figure 2. Voltage Reference vs Junction Temperature
TPS57060-Q1 fs_tj_lvsa25.gif
Figure 4. Switching Frequency vs Junction Temperature
TPS57060-Q1 fs_rt_clk2_lvsa25.gif
Figure 6. Switching Frequency vs RT/CLK Resistance Low-Frequency Range
TPS57060-Q1 ea2_tj_lvsa25.gif
Figure 8. EA Transconductance vs Junction Temperature
TPS57060-Q1 ic_tj_lvsa25.gif
Figure 10. EN Pin Current vs Junction Temperature
TPS57060-Q1 ss_tr_tj_lvsa25.gif
Figure 12. SS/TR Charge Current vs Junction Temperature
TPS57060-Q1 fs_vsense_lvsa25.gif
Figure 14. Switching Frequency vs VSENSE
TPS57060-Q1 icc_vi_lvsa25.gif
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
TPS57060-Q1 icc_vi2_lvsa25.gif
Figure 18. VIN Supply Current vs Input Voltage
TPS57060-Q1 pwrgd_tj_lvsa25.gif
Figure 20. PWRGD Threshold vs Junction Temperature
TPS57060-Q1 uvlo_tj_lvsa25.gif
Figure 22. Input Voltage (UVLO) vs Junction Temperature
TPS57060-Q1 offset_tj_lvsa25.gif
Figure 24. SS/TR to VSENSE Offset vs Temperature