SLUSDL0A January   2020  – March 2020 TPS59603-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO Protection
      2. 7.3.2 PWM Pin
      3. 7.3.3 SKIP Pin
        1. 7.3.3.1 Zero Crossing (ZX) Operation
      4. 7.3.4 Adaptive Dead-Time Control and Shoot-Through Protection
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Recommendation
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DSG Package
8-Pin WSON
Top View
TPS59603-Q1 pinout_dsg8_slusba6.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
BST 1 I High-side N-channel FET bootstrap voltage input; power supply for high-side driver
DRVH 8 O High-side N-channel gate drive output
DRVL 5 O Synchronous low-side N-channel gate drive output
GND 6 G Synchronous low-side N-channel gate drive return and device reference
PWM 2 I PWM input. A tri-state voltage on this pin turns off both the high-side (DRVH) and low-side drivers (DRVL)
SKIP 3 I When SKIP is LO, the zero crossing comparator is active. The power chain enters discontinuous conduction mode when the inductor current reaches zero. When SKIP is HI, the zero crossing comparator is disabled, and the driver outputs follow the PWM input. A tri-state voltage on SKIP puts the driver into a very-low power state.
SW 7 I/O High-side N-channel gate drive return. Also, zero-crossing sense input
VDD 4 I 5-V power supply input; decouple to GND with a ceramic capacitor with a value of 1 µF or greater
Thermal Pad G Tie to system GND plane with multiple vias
(1) I = Input, O = Output, G = Ground