SLVSE52A September   2018  – November 2018 TPS61088-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable and Start-up
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Adjustable Switching Frequency
      4. 8.3.4 Adjustable Peak Current Limit
      5. 8.3.5 Overvoltage Protection
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation
        1. 8.4.1.1 PWM Mode
        2. 8.4.1.2 PFM Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design with WEBENCH Tools
        2. 9.2.2.2 Setting Switching Frequency
        3. 9.2.2.3 Setting Peak Current Limit
        4. 9.2.2.4 Setting Output Voltage
        5. 9.2.2.5 Inductor Selection
        6. 9.2.2.6 Input Capacitor Selection
        7. 9.2.2.7 Output Capacitor Selection
        8. 9.2.2.8 Loop Stability
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design with WEBENCH Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RHL Package
20 Pin VQFN With Thermal Pad
Top View
TPS61088-Q1 po_LVSCM8.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
VCC 1 O Output of the internal regulator. A ceramic capacitor of more than 1 µF is required between this pin and ground.
EN 2 I Enable logic input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode.
FSW 3 I The switching frequency is programmed by a resister between this pin and the SW pin.
SW 4, 5, 6, 7 I The switching node pin of the converter. It is connected to the drain of the internal low-side power MOSFET and the source of the internal high-side power MOSFET.
BOOT 8 O Power supply for high-side MOSFET gate driver. A ceramic capacitor of 0.1 µF must be connected between this pin and the SW pin
VIN 9 I IC power supply input
SS 10 O Soft-start programming pin. An external capacitor sets the ramp rate of the internal error amplifier's reference voltage during soft-start
NC 11, 12 — No connection inside the device. Connect these two pins to ground plane on the PCB for good thermal dissipation
MODE 13 I Operation mode selection pin for the device in light load condition. When this pin is connected to ground, the device works in PWM mode. When this pin is left floating, the device works in PFM mode.
VOUT 14, 15, 16 O Boost converter output
FB 17 I Voltage feedback. Connect to the center tape of a resistor divider to program the output voltage.
COMP 18 O Output of the internal error amplifier, the loop compensation network should be connected between this pin and the AGND pin.
ILIM 19 O Adjustable switch peak current limit. An external resister should be connected between this pin and the AGND pin.
AGND 20 — Signal ground of the IC
PGND 21 — Power ground of the IC. It is connected to the source of the low-side MOSFET.