SLVS873D June   2015  – April 2016 TPS61098 , TPS610981 , TPS610982 , TPS610985 , TPS610986 , TPS610987

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Boost Controller Operation
      2. 8.3.2 Pass-Through Operation
      3. 8.3.3 LDO / Load Switch Operation
      4. 8.3.4 Start Up and Power Down
      5. 8.3.5 Over Load Protection
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation Modes by MODE Pin
        1. 8.4.1.1 Active Mode
        2. 8.4.1.2 Low Power Mode
      2. 8.4.2 Burst Mode Operation under Light Load Condition
      3. 8.4.3 Pass-Through Mode Operation
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 VMAIN to Power MCU and VSUB to Power Subsystem
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Device Choice
          2. 9.2.1.2.2 Maximum Output Current
          3. 9.2.1.2.3 Inductor Selection
          4. 9.2.1.2.4 Capacitor Selection
          5. 9.2.1.2.5 Control Sequence
        3. 9.2.1.3 Application Curves
      2. 9.2.2 VMAIN to Power the System in Low Power Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 VSUB to Power the System in Active Mode
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS61098x is an ultra low power solution for products powered by either a one-cell or two-cell alkaline, NiCd or NiMH, one-cell coin cell or one-cell Li-Ion or Li-polymer battery. It integrates either a Low-dropout Linear Regulator (LDO) or a load switch with a boost converter and provides dual output rails. The V(MAIN) rail is the output of the boost converter. It is an always-on output and can only be turned off by removing input voltage. The V(SUB) rail is the output of the integrated LDO or load switch, and it can be turned off by pulling the MODE pin low.

9.2 Typical Applications

9.2.1 VMAIN to Power MCU and VSUB to Power Subsystem

The TPS61098x suits for low power systems very well, especially for the system which spends the most of time in sleep mode and wakes up periodically to sense or transmit signals. For this kind of application, the boost output V(MAIN) can be used as an always-on supply for the main system, such as an MCU controller, and the LDO or load switch output V(SUB) is used to power peripheral devices or subsystem.

As shown in Figure 57, the MCU can control both of the subsystem and the TPS61098x. When the system goes into sleep mode, the MCU can disable the subsystem first, and then force the TPS61098x enter into Low Power mode, where the VSUB rail is disconnected but the V(MAIN) rail still powers the MCU with only 300 nA quiescent current. When the system wakes up, the MCU pulls the MODE pin of TPS61098x high first to turn on the VSUB rail, and then enables the subsystem. In this way, the system can benefit both of the enhanced transient response performance in active mode and the ultra-low quiescent current in sleep mode.

TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 app_appinfo_981.gif Figure 57. Typical Application of TPS610981 to Power Low Power System

9.2.1.1 Design Requirements

  • 3.3 V V(MAIN) rail to power MCU with 15 mA load current, 3 V V(SUB) rail to power subsystem with 10 mA load current
  • Power source, single-cell alkaline battery (0.7 V to 1.65 V range)
  • Greater than 90% conversion efficiency

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Device Choice

In the TPS61098x family, different versions are provided. Refer to Device Comparison Table for version details and select the right version for target applications. It is OK to use only one output rail, either V(MAIN) or V(BUS), as long as it suits the application.

In this example, dual rails of 3.3 V and 3 V are required to power both MCU and subsystem, so the TPS610981 is selected.

9.2.1.2.2 Maximum Output Current

For the boost converter, it provides output current for both V(MAIN) and V(SUB) rails. Its maximum output capability is determined by the input to output ratio and the current limit of the boost converter and can be estimated by Equation 3.

Equation 3. TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 q_maxIout.gif

where η is the boost converter power efficiency estimation, and 50 mA is half of the inductor current ripple value. Minimum input voltage, maximum boost output voltage and minimum current limit ILIM_BST should be used as the worst case condition for the estimation.

Internal current limit is also implemented for the integrated LDO/load switch. So the maximum output current of VSUB rail should be lower than ILIM_SUB, which has 200 mA minimum value. For LDO version, the maximum output current is also limited by its input to output headroom, that is V(MAIN) - V(SUB). Make sure the headroom voltage is enough to support the load current. Please refer to Electrical Characteristics for the dropout voltage information.

In this example, assume the power efficiency is 80% (lower than typical value for the worst case estimation), so the calculated maximum output current of the boost converter is 50.9 mA, which satisfies the application requirements (15 mA + 10 mA). The load of VSUB rail is 10 mA, which is well below the V(SUB) rail current limit and the dropout voltage is also within the headroom.

9.2.1.2.3 Inductor Selection

Because the selection of the inductor affects steady state operation, transient behavior, and loop stability, the inductor is the most important component in power regulator design. There are three important inductor specifications, inductor value, saturation current, and dc resistance (DCR).

The TPS61098x is designed to work with inductor values between 2.2 µH and 4.7 µH. The inductance values affects the switching frequency ƒ in continuous current operation, which is proportional to 1/L as shown in Equation 4.

Equation 4. TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 q_freq.gif

The inductor current ripple is fixed to 100mA typical value by internal design, but it can be affected by the inductor value indirectly. Normally when a smaller inductor value is applied, the inductor current ramps up and down more quickly, so the current ripple becomes bigger because the internal current comparator has some delay to respond. So if smaller inductor peak current is required in applications, a higher inductor value can be tried. However, the TPS61098x is optimized to work within a range of L and C combinations. The LC output filter inductance and capacitance must be considered together. The output capacitor sets the corner frequency of the converter while the inductor creates a Right-Half-Plane-Zero degrading the stability of the converter. Consequently with a larger inductor, a bigger capacitor normally should be used to ensure the same L/C ratio thus a stable loop.

Having selected an inductance value, the peak current for the inductor in steady-state operation varies as a function of the load, the input and output voltages and can be estimated using Equation 5.

Equation 5. TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 q_Ilmax.gif

where, 80% can be used for the boost converter power efficiency estimation, 100 mA is the typical inductor current ripple value and 50mA is half of the ripple value, which may be affected a little bit by inductor value. Equation 5 provides a suitable inductor current rating by using minimum input voltage, maximum boost output voltage and maximum load current for the calculation. Load transients and error conditions may cause higher inductor currents.

Equation 6 provides an easy way to estimate whether the device will work in continuous or discontinuous operation depending on the operating points. As long as the Equation 6 is true, continuous operation is typically established. If Equation 6 becomes false, discontinuous operation is typically established.

Equation 6. TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 q_bndry.gif

Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the converter. This could eventually harm the device and reduce it's reliability.

In this example, the maximum load for the boost converter is 25 mA, and the minimum input voltage is 0.7 V, and the efficiency under this condition can be estimated at 80%, so the boost converter works in continuous operation by the calculation. The inductor peak current is calculated as 197 mA. To leave some margin, a 4.7 µH inductor with at least 250 mA saturation current is recommended for this application.

Table 1 also lists the recommended inductor for the TPS61098x device.

Table 1. List of Inductors

INDUCTANCE [µH] ISAT [A] IRMS [A] DC RESISTANCE [mΩ] PART NUMBER MANUFACTURER
4.7 0.86 1.08 168 VLF302510MT-4R7M TDK
4.7 0.57 0.95 300 VLF252010MT-4R7M TDK
2.2 1.23 1.5 84 VLF302510MT-2R2M TDK
2.2 0.83 0.92 120 VLF252010MT-2R2M TDK

9.2.1.2.4 Capacitor Selection

For best output and input voltage filtering, low ESR X5R or X7R ceramic capacitors are recommended.

The input capacitor minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail for the device. An input capacitor value of at least 10 μF is recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. A ceramic capacitor placed as close as possible to the VIN and GND pins of the IC is recommended. For applications where line transient is expected, an input filter composed of 400-Ω resistor and 0.1-µF capacitor as shown in Figure 57 is mandatory to avoid interference to internal pass-through threshold comparison circuitry.

For the output capacitor of VMAIN pin, small ceramic capacitors are recommended, placed as close as possible to the VMAIN and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which cannot be placed close to the IC, the use of a small ceramic capacitor with a capacitance value of around 2.2 μF in parallel to the large one is recommended. This small capacitor should be placed as close as possible to the VMAIN and GND pins of the IC. The recommended typical output capacitor values are 10 μF and 22 µF (nominal values).

For LDO version, like all low dropout regulators, VSUB rail requires an output capacitor connected between VSUB and GND pins to stabilize the internal control loop. Ceramic capacitor of 10 µF (nominal value) is recommended for most applications. If the V(SUB) drop during load transient is much cared, higher capacitance value up to 22 µF is recommended to provide better load transient performance. Capacitor below 10 µF is only recommended for light load operation. For load switch version, capacitor of 10x smaller value than capacitor at VMAIN pin is recommended to minimize the voltage drop caused by charge sharing when the load switch is turned on.

When selecting capacitors, ceramic capacitor’s derating effect under bias should be considered. Choose the right nominal capacitance by checking capacitor's DC bias characteristics. In this example, GRM188R60J106ME84D, which is a 10 µF ceramic capacitor with high effective capacitance value at DC biased condition, is selected for both VMAIN and VSUB rails. The load transient response performance is shown in Application Curves section.

For load switch version, VSUB rails requires an output capacitor connected between VSUB and GND pins. Ceramic capacitor of 1 µF (nominal value) is recommended for most applications.

9.2.1.2.5 Control Sequence

In this example, the MCU is powered by the boost output V(MAIN) and the subsystem is powered by the LDO V(SUB). MCU controls both of the TPS610981 and subsystem. The control sequence as shown in Figure 58 is recommended.

TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Ctrl_Seq.gif Figure 58. System Control Sequence

When the system is waking up, the MCU wakes up itself first, and it then pulls the MODE pin of TPS610981 to high to turned on the V(SUB) rail. TPS610981 enters into Active mode and gets ready to provide power to the subsystem. Then the MCU enables the subsystem.

When the system is entering into sleep mode, the MCU disables the subsystem first and then pulls the MODE pin to low to turn off the V(SUB), so the subsystem is disconnected from the supply to minimize the current drain. TPS610981 enters into Low Power mode and the VMAIN rail still powers the MCU with only 300 nA quiescent current. The MCU enters into sleep mode itself finally.

9.2.1.3 Application Curves

TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig 1.png
TPS610981 I(MAIN) = 1 mA I(SUB) = 0 mA
MODE = L VIN = 1.5 V
Figure 59. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig 3.png
TPS610981 I(MAIN) = 100 mA I(SUB) = 0 mA
MODE = L VIN = 1.5 V
Figure 61. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig 5.png
TPS610981 I(MAIN) = 0 mA I(SUB) = 10 mA
MODE = H VIN = 1.5 V
Figure 63. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig._67_SW_986_1mA.png
TPS610896 I(MAIN) = 0 mA I(SUB) = 1 mA
MODE = H VIN = 1.5V
Figure 65. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig_ 69_SW_986_100mA.png
TPS610896 I(MAIN) = 0 mA I(SUB) = 100 mA
MODE = H VIN = 1.5V
Figure 67. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=H_loadtran_44.png
TPS610981 VIN = 2.5 V I(SUB) = 0 mA
MODE = H I(MAIN) = 0 mA to 50 mA, 5 µs rising/falling edge
Figure 69. Load Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=L_linetran_22.png
TPS610981 I(MAIN) = 20 mA I(SUB) = 0 mA
MODE = L VIN = 2 V to 2.5 V, 10 µs rising/falling edge
Figure 71. Line Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=H_linetran_24.png
TPS610981 I(MAIN) = 0 mA I(SUB) = 20 mA
MODE = H VIN = 2 V to 2.5 V, 10 µs rising/falling edge
Figure 73. Line Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=H_loadreg_49.png
TPS610981 VIN = 1.5 V I(MAIN) = 0 mA
MODE = H I(SUB) = 0 mA to 120 mA to 0 mA, ramp up and down
Figure 75. Load Regulation
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_Mode toggle_30.png
TPS610981 R(MAIN) = 1 kΩ R(SUB) = open load
MODE pin toggling
Figure 77. Mode Toggling
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=H_startup_32.png
TPS610981 R(MAIN) = 1 kΩ R(SUB) = 1 kΩ
VIN = 1.5 V MODE connected to VMAIN
Figure 79. Startup
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig 2.png
TPS610981 I(MAIN) = 10 mA I(SUB) = 0 mA
MODE = L VIN = 1.5 V
Figure 60. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig 4.png
TPS610981 I(MAIN) = 0 mA I(SUB) = 1 mA
MODE = H VIN = 1.5 V
Figure 62. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig 6.png
TPS610981 I(MAIN) = 0 mA I(SUB) = 100 mA
MODE = H VIN = 1.5V
Figure 64. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig._68_SW_986_10mA.png
TPS610896 I(MAIN) = 0 mA I(SUB) = 10 mA
MODE = H VIN = 1.5V
Figure 66. Switching Waveforms
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=L_loadtran_45.png
TPS610981 VIN = 2.5 V I(SUB) = 0 mA
MODE = L I(MAIN) = 0 mA to 50 mA, 5 µs rising/falling edge
Figure 68. Load Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_ldo load tran_46.png
TPS610981 VIN = 2.5 V I(MAIN) = 0 mA
MODE = H I(SUB) = 0 mA to 50 mA, 5 µs rising/falling edge
Figure 70. LDO Load Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=H_linetran_23.png
TPS610981 I(MAIN) = 20 mA I(SUB) = 0 mA
MODE = H VIN = 2 V to 2.5 V, 10 µs rising/falling edge
Figure 72. Line Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=L_loadreg_50.png
TPS610981 VIN = 1.5 V I(SUB) = 0 mA
MODE = L I(MAIN) = 0 mA to 120 mA to 0 mA, ramp up and down
Figure 74. Load Regulation
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=H_linereg_35.png
TPS610981 I(MAIN) = 0 mA I(SUB) = 30 mA
MODE = H VIN = 0.7 V to 4.5 V, ramp up and down
Figure 76. Line Regulation
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 981_M=L_startup_31.png
TPS610981 R(MAIN) = 3 kΩ VIN = 0.7 V
MODE connected to GND
Figure 78. Startup
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 Fig_82_Startup986.png
TPS610896 R(MAIN) = 1 kΩ R(SUB) = 1 kΩ
VIN = 1.5 V C(SUB) = 1 µF
MODE connected to VMAIN
Figure 80. Startup

9.2.2 VMAIN to Power the System in Low Power Mode

If only one power supply is needed for the whole system, users can easily leave the VSUB pin float and only use the VMAIN rail as the power supply. In this case, the TPS61098x functions as a standard boost converter. If enhanced load transient performance is needed when the system works in Active mode, the controller can control the MODE pin to switch the TPS61098x between the Active mode and Low Power mode. If the ultra-low Iq is critical for the application, users can connect the MODE pin to GND so the TPS61098x keeps working in Low Power mode with only 300 nA quiescent current. Below shows a typical application where the TPS61098 is used in Low Power mode to generate 2.2 V with only 300 nA Iq to power the whole system.

TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 app_appinfo_98_lpmode.gif Figure 81. Typical Application of TPS61098 VMAIN to Power the System in Low Power Mode

9.2.2.1 Design Requirements

  • 2.2 V V(MAIN) to power the whole system
  • Power source, single-cell alkaline battery (0.7 V to 1.65 V range)
  • ≥ 80% conversion efficiency at 10 µA load

9.2.2.2 Detailed Design Procedure

Refer to the Detailed Design Procedure section for the detailed design steps.

9.2.2.3 Application Curves

TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 98_M=L_loadtran_43.png
TPS61098 VIN = 1.5 V
MODE = L I(MAIN) = 50 mA to 100 mA, 5 µs
rising/falling edge
Figure 82. Load Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 98_M=L_startup_34.png
TPS61098 R(MAIN) = 3 kΩ
MODE connected to GND VIN = 0.7 V
Figure 84. Startup
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 098_M=L_linetran_20.png
TPS61098 I(MAIN) = 100 mA I(SUB) = 0 mA
MODE = L VIN = 1.2 V to 1.8 V, 10 µs
rising/falling edge
Figure 83. Line Transient Response

9.2.3 VSUB to Power the System in Active Mode

In some applications, the system controller can be powered by the battery directly, but a buck-boost or a boost converter with an LDO is needed to provide a quiet power supply for a subsystem like a sensor. In this type of application, the TPS61098x can be used to replace the discrete boost converter and the LDO, providing a compact solution to simplify the system design and save the PCB space. The LDO can be turned on and off by the MODE pin. When the MODE pin is pulled low, the LDO is turned off to disconnect the load, and the TPS61098x also enters into Low Power mode to save power consumption. Figure 85 shows an application where the VSUB of the TPS61098 is used to supply the 3.1 V for a sensor in a system. The boost converter of the TPS61098 outputs 4.3 V and provides enough headroom for the LDO operation.

TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 app_appinfo_98_actmode.gif Figure 85. Typical Application of TPS61098 VSUB to Power the System in Active Mode

9.2.3.1 Design Requirements

  • 3.1 V rail to power a sensor
  • Power source, single-cell li-ion battery (2.7 V to 4.3 V range)

9.2.3.2 Detailed Design Procedure

Refer to the Detailed Design Procedure section for the detailed design steps.

9.2.3.3 Application Curves

TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 98_ldo load tran_48.png
TPS61098 VIN = 3.6 V I(MAIN) = 0 mA
MODE = H I(SUB) = 0 mA to 50 mA , 5 µs rising/falling edge
Figure 86. LDO Load Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 LDO line tran_982_M=L_73.png
TPS610982 I(MAIN) = 0 mA I(SUB) = 100 mA
MODE = L VIN = 2 V to 2.5 V, 10 µs rising/falling edge
Figure 88. Line Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 LDO load tran_982_M=L_76.png
TPS610982 VIN = 2.5 V I(MAIN) = 0 mA
MODE = L I(SUB) = 50 mA to 100 mA , 5 µs rising/falling edge
Figure 90. LDO Load Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 98_Mode toggle_29.png
TPS61098 R(MAIN) = 10 kΩ R(SUB) = 3 kΩ
MODE pin toggling
Figure 92. MODE Toggling
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 startup_982_M=L_72.png
TPS610982 R(MAIN) = 1 kΩ R(SUB) = 1 kΩ
MODE connected to GND VIN = 1.5 V
Figure 94. Startup
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 98_M=H_linetran_21.png
TPS61098 I(MAIN) = 0 mA I(SUB) = 100 mA
MODE = H VIN = 2.7 V to 3.2 V, 5 µs rising/falling edge
Figure 87. Line Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 LDO line tran_982_M=H_74.png
TPS610982 I(MAIN) = 0 mA I(SUB) = 100 mA
MODE = H VIN = 2 V to 2.5 V, 10 µs rising/falling edge
Figure 89. Line Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 LDO load tran_982_M=H_75.png
TPS610982 VIN = 2.5 V I(MAIN) = 0 mA
MODE = H I(SUB) = 50 mA to 100 mA , 5 µs rising/falling edge
Figure 91. LDO Load Transient Response
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 98_M=H_startup_33.png
TPS61098 R(MAIN) = 1 kΩ R(SUB) = 1 kΩ
MODE connected to VMAIN VIN = 3.6 V
Figure 93. Startup
TPS61098 TPS610981 TPS610982 TPS610985 TPS610986 TPS610987 startup_982_M=H_71.png
TPS610982 R(MAIN) = 1 kΩ R(SUB) = 1 kΩ
MODE connected to VMAIN VIN = 1.5 V
Figure 95. Startup