SLVSAX2B September 2011 – June 2020 TPS61170-Q1
PRODUCTION DATA.
The TPS61170-Q1 has an external compensation, COMP pin, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external resistor R3 and ceramic capacitor C3 are connected to COMP pin to provide a pole and a zero. This pole and zero, along with the inherent pole of a current mode control boost converter, determine the close loop frequency response. This is important to a converter stability and transient response.
The following equations summarize the poles, zeros and DC gain of a TPS61170-Q1 boost converter with ceramic output capacitor (C2), as shown in the block diagram. They include the dominant pole (fP1), the output pole (fP2) of a boost converter, the right-half-plane zero (fRHPZ) of a boost converter, the zero (fZ) generated by R3 and C3, and the DC gain (A).
where
These equations help generate a simple bode plot for TPS61170-Q1 loop analysis.
Increasing R3 or reducing C3 increases the close loop bandwidth which improves the transient response. Adjusting R3 and C3 in opposite directions increase the phase, and help loop stability. For many of the applications, the recommended value of 10 kΩ and 680 pF makes an ideal compromise between transient response and loop stability. To optimize the compensation, use C3 in the range of 100 pF to 10 nF, and R3 of 10 kΩ. See the TI application report, SLVA319, for thorough analysis and description of the boost converter small signal model and compensation design.