SLVSCN9B December   2014  – June 2020 TPS61175-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switching Frequency
      2. 7.3.2 Soft Start
      3. 7.3.3 Overcurrent Protection
      4. 7.3.4 Enable and Thermal Shutdown
      5. 7.3.5 Under Voltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum ON Time and Pulse Skipping
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Determining the Duty Cycle
        2. Selecting the Inductor
        3. Computing the Maximum Output Current
        4. Setting Output Voltage
        5. Setting the Switching Frequency
        6. Setting the Soft Start Time
        7. Selecting the Schottky Diode
        8. Selecting the Input and Output Capacitors
        9. Compensating the Small Signal Control Loop
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Compensating the Small Signal Control Loop

All continuous mode boost converters have a right half plane zero (ƒRHPZ) due to the inductor being removed from the output during charging. In a traditional voltage mode controlled boost converter, the inductor and output capacitor form a small signal double pole. For a negative feedback system to be stable, the fed back signal must have a gain less than 1 before having 180 degrees of phase shift. With its double pole and RHPZ all providing phase shift, voltage mode boost converters are a challenge to compensate. In a converter with current mode control, there are essentially two loops, an inner current feedback loop created by the inductor current information sensed across RSENSE (40 mΩ) and the output voltage feedback loop. The inner current loop allows the switch, inductor and modulator to be lumped together into a small signal variable current source controlled by the error amplifier, as shown in Figure 9.

TPS61175-Q1 ccm_boost_lvs892.gifFigure 9. Small Signal Model of a Current Mode Boost in CCM

The new power stage, including the slope compensation, small signal model becomes:

Equation 12. TPS61175-Q1 eq_gpw_lvs892.gif


Equation 13. TPS61175-Q1 eq_fp_lvs892.gif
Equation 14. TPS61175-Q1 eq2_fp_lvs892.gif
Equation 15. TPS61175-Q1 eq_frhpz_lvs892.gif


Equation 16. TPS61175-Q1 eq_he_lvs892.gif

He(s) models the inductor current sampling effect as well as the slope compensation effect on the small signal response.


If Se slope dominates Sn, that is, when the inductance is oversized in order to give ripple current much smaller than the recommended 0.2 – 0.4 times the average input current, then the converter behaves more like a voltage mode converter, and the above model no longer holds.

The slope compensation in TPS61175-Q1 is shown as follow

Equation 17. TPS61175-Q1 eq_sn_lvs892.gif
Equation 18. TPS61175-Q1 eq_sn2_lvs892.gif
Where R4 is the frequency setting resistor

Figure 10 shows a bode plot of a typical CCM boost converter power stage

TPS61175-Q1 pwr_plot_lvs892.gifFigure 10. Bode Plot of Power Stage Gain and Phase

The TPS61175-Q1 COMP pin is the output of the internal trans-conductance amplifier. Equation 19 shows the equation for feedback resistor network and the error amplifier.

Equation 19. TPS61175-Q1 eq_h_lvs892.gif

where GEA and REA are the amplifier’s trans-conductance and output resistance located in the Electrical Characteristics table.

Equation 20. TPS61175-Q1 eq_fp1_lvs892.gif
Equation 21. TPS61175-Q1 eq_fp2_lvs892.gif
C5 is optional and can be modeled as 10 pF stray capacitance.


Equation 22. TPS61175-Q1 eq_fz_lvs892.gif

Figure 11 shows a typical bode plot for transfer function H(s).

TPS61175-Q1 amp_plt_lvs892.gifFigure 11. Bode Plot of Feedback Resistors and Compensated Amplifier Gain and Phase

The next step is to choose the loop crossover frequency, fC. The higher in frequency that the loop gain stays above zero before crossing over, the faster the loop response will be and therefore the lower the output voltage will droop during a step load. It is generally accepted that the loop gain cross over no higher than the lower of either 1/5 of the switching frequency, fSW, or 1/3 of the RHPZ frequency, fRHPZ. To approximate a single pole roll-off up to fP2, select R3 so that the compensation gain, KCOMP, at fC on Figure 11 is the reciprocal of the gain, KPW, read at frequency fC from the Figure 10 bode plot or more simply

KCOMP(fC) = 20 × log(GEA × R3 × R2/(R2+R1)) = 1/KPW(fC)

This makes the total loop gain, T(s) = GPS(s) × HEA(s), zero at the fC. Then, select C4 so that fZ ≅ fC/10 and optional fP2> fC *10. Following this method should lead to a loop with a phase margin near 45 degrees. Lowering R3 while keeping fZ ≅ fC/10 increases the phase margin and therefore increases the time it takes for the output voltage to settle following a step load.

In the TPS61175-Q1, if the FB pin voltage changes suddenly due to a load step on the output voltage, the error amplifier increases its transconductance for 8-ms in an effort to speed up the IC’s transient response and reduce output voltage droop due to the load step. For example, if the FB voltage decreases 10-mV due to load change, the error amplifier increases its source current through COMP by 5 times; if FB voltage increases 11-mV, the sink current through COMP is increased to 3.5 times normal value. This feature often results in saw tooth ringing on the output voltage, shown as Figure 13. Designing the loop for greater than 45 degrees of phase margin and greater than 10db gain margin minimizes the amplitude of this ringing. This feature is disabled during soft start.