SLVSCN9B December   2014  – June 2020 TPS61175-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switching Frequency
      2. 7.3.2 Soft Start
      3. 7.3.3 Overcurrent Protection
      4. 7.3.4 Enable and Thermal Shutdown
      5. 7.3.5 Under Voltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum ON Time and Pulse Skipping
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Determining the Duty Cycle
        2. Selecting the Inductor
        3. Computing the Maximum Output Current
        4. Setting Output Voltage
        5. Setting the Switching Frequency
        6. Setting the Soft Start Time
        7. Selecting the Schottky Diode
        8. Selecting the Input and Output Capacitors
        9. Compensating the Small Signal Control Loop
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Selecting the Input and Output Capacitors

The output capacitor is mainly selected to meet the requirements for the output ripple and load transient. Then the loop is compensated for the output capacitor selected. The output ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by

Equation 10. TPS61175-Q1 eq_cout_lvs892.gif

where, Vripple= peak to peak output ripple. The additional output ripple component caused by ESR is calculated using:

Vripple_ESR = I × RESR

Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used.

The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated by Equation 11.

Equation 11. TPS61175-Q1 eq_cout2_lvs892.gif


  • ΔITRAN is the transient load current step
  • ΔVTRAN is the allowed voltage dip for the load current step
  • fLOOP-BW is the control loop bandwidth (that is, the frequency where the control loop gain crosses zero).

Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the switching frequency. So the effective capacitance is significantly lower. The DC bias can also significantly reduce capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, one must add margin on the voltage rating to ensure adequate capacitance at the required output voltage.

For a typical boost converter implementation, at least 4.7μF of ceramic input and output capacitance is recommended. Additional input and output capacitance may be required to meet ripple and/or transient requirements.

The popular vendors for high value ceramic capacitors are:


Murata (