SLVSFP3C August   2020  – March 2022 TPS61288

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable and Start-up
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Switching Peak Current Limit
      4. 8.3.4 Overvoltage Protection
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM
      2. 8.4.2 PFM
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Output Voltage
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Loop Stability
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-B817845B-BAF4-40F0-8812-036745133B07-low.gif Figure 6-1 11-Pin RQQ VQFN Package (Top View)
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NUMBER
FB 1 I Voltage feedback. Connect to the center tape of a resistor divider to program the output voltage.
COMP 2 O Output of the internal error amplifier, the loop compensation network should be connected between this pin and the AGND pin.
PGND 3 PWR Power ground of the IC. It is connected to the source of the low-side MOSFET.
SW 4,9 PWR The switching node pin of the converter. It is connected to the drain of the internal low-side power MOSFET and the source of the internal high-side power MOSFET.
VOUT 5 PWR Boost converter output
EN 6 I Enable logic input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode.
VIN 7 I IC power supply input
BST 8 O Power supply for high-side MOSFET gate driver. A ceramic capacitor of 0.1 µF must be connected between this pin and the SW pin.
AGND 10 - Signal ground of the IC
VCC 11 O Output of the internal regulator. A ceramic capacitor of more than 1.0 µF is required between this pin and ground.