SLVSAJ0F November   2011  – October 2021 TPS62140 , TPS62140A , TPS62141 , TPS62142 , TPS62143

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Enable/Shutdown (EN)
      2. 8.3.2 Soft-Start/Tracking (SS/TR)
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Pin-Selectable Output Voltage (DEF)
      5. 8.3.5 Frequency Selection (FSW)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse-Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short Circuit Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 External Component Selection
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Capacitor Selection
            1. 9.2.2.2.2.1 Output Capacitor
            2. 9.2.2.2.2.2 Input Capacitor
            3. 9.2.2.2.2.3 Soft-Start Capacitor
        3. 9.2.2.3 Tracking Function
        4. 9.2.2.4 Output Filter and Loop Stability
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 LED Power Supply
      2. 9.3.2 Active Output Discharge
      3. 9.3.3 Inverting Power Supply
      4. 9.3.4 Various Output Voltages
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-D3F3A8D3-9C05-4CF9-B1D3-6E6EE07E41B7-low.gifFigure 6-1 16-Pin VQFNRGT Package(Top View)
Table 6-1 Pin Functions
PIN(1) I/O DESCRIPTION
NO. NAME
1,2,3 SW O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and the output capacitor.
4 PG O Output power good (high = VOUT ready, low = VOUT below nominal regulation); open drain (requires pullup resistor)
5 FB I Voltage feedback of the adjustable version. Connect a resistive voltage divider to this pin. It is recommended to connect FB to AGND on fixed output voltage versions for improved thermal performance.
6 AGND Analog ground. Must be connected directly to the exposed thermal pad and common ground plane.
7 FSW I Switching frequency select (low ≈ 2.5 MHz, high ≈ 1.25 MHz(2) for typical operation)(3)
8 DEF I Output voltage scaling (low = nominal, high = nominal + 5%)(3)
9 SS/TR I Soft-start/tracking [in. An external capacitor connected to this pin sets the internal voltage reference rise time. It can be used for tracking and sequencing.
10 AVIN I Supply voltage for control circuitry. Connect to the same source as PVIN.
11,12 PVIN I Supply voltage for power stage. Connect to the same source as AVIN.
13 EN I Enable input (high = enabled, low = disabled)(3)
14 VOS I Output voltage sense pin and connection for the control loop circuitry
15,16 PGND Power ground. Must be connected directly to the exposed thermal pad and common ground plane.
Exposed Thermal Pad Must be connected to AGND (pin 6), PGND (pin 15, 16), and common ground plane. See Figure 11-1. Must be soldered to achieve appropriate power dissipation and mechanical reliability.
(1) For more information about connecting pins, see Section 8 and Section 9.
(2) Connect FSW to VOUT or PG in this case.
(3) An internal pulldown resistor keeps the logic level low, if pin is floating.