SLUSDM0J May   2020  – November 2023 TPS628501-Q1 , TPS628502-Q1 , TPS628503-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Schematic
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precise Enable (EN)
      2. 8.3.2 COMP/FSET
      3. 8.3.3 MODE / SYNC
      4. 8.3.4 Spread Spectrum Clocking (SSC)
      5. 8.3.5 Undervoltage Lockout (UVLO)
      6. 8.3.6 Power-Good Output (PG)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (PWM/PFM)
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short Circuit Protection
      5. 8.4.5 Foldback Current Limit and Short-Circuit Protection
      6. 8.4.6 Output Discharge
      7. 8.4.7 Input Overvoltage Protection
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Programming the Output Voltage
      2. 9.1.2 External Component Selection
        1. 9.1.2.1 Inductor Selection
      3. 9.1.3 Capacitor Selection
        1. 9.1.3.1 Input Capacitor
        2. 9.1.3.2 Output Capacitor
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Fixed Output Voltage Versions
      2. 9.3.2 Synchronizing to an External Clock
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over operating junction remperature range (TJ = -40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = VIN, no load, device not switching, MODE = GND, VOUT = 0.6 V 17 36 μA
ISD Shutdown current EN = GND, Nominal value at TJ = 25°C, Max value at TJ = 150°C 1.5 48 μA
VUVLO Undervoltage lock out threshold VIN rising 2.45 2.6 2.7 V
VIN falling 2.1 2.5 2.6 V
TJSD Thermal shutdown threshold TJ rising 170 °C
Thermal shutdown hysteresis TJ falling 15 °C
CONTROL and INTERFACE
VEN,IH Input threshold voltage at EN, rising edge 1.05 1.1 1.15 V
VEN,IL Input threshold voltage at EN, falling edge 0.96 1.0 1.05 V
VIH High-level input-threshold voltage at MODE/SYNC 1.1 V
IEN,LKG Input leakage current into EN VIH = VIN or VIL = GND 125 nA
VIL Low-level input-threshold voltage at MODE/SYNC 0.3 V
ILKG Input leakage current into MODE/SYNC 100 nA
tDelay Enable delay time Time from EN high to device starts switching; VIN applied already 135 200 520 µs
tDelay Enable delay time Time from EN high to device starts switching; VIN applied already,
VIN ≥ 3.3 V		 480 µs
tRamp Output voltage ramp time Time from device starts switching to power good; device not in current limit 0.8 1.3 1.8 ms
tRamp Output voltage ramp time Time from device starts switching to power good; device not in current limit 90 150 210 µs
fSYNC Frequency range on MODE/SYNC pin for synchronization 1.8 4 MHz
Duty cycle of synchronization signal at MODE/SYNC 20 80 %
Time to lock to external frequency 50 µs
resistance from COMP/FSET to GND for logic low internal frequency setting with
f = 2.25 MHz		 0 2.5 kΩ
Voltage on COMP/FSET for logic high internal frequency setting with
f = 2.25 MHz		 VIN V
VTH_PG UVP power good threshold voltage;
DC level		 rising (%VFB) 92 95 98 %
VTH_PG UVP power good threshold voltage;
DC level		 falling (%VFB) 87 90 93 %
VTH_PG OVP power good threshold voltage;
DC level		 rising (%VFB) 107 110 113 %
OVP power good threshold voltage;
DC level		 falling (%VFB) 104 107 111 %
VPG,OL Low-level output voltage at PG ISINK_PG = 2 mA 0.07 0.3 V
IPG,LKG Input leakage current into PG VPG = 5 V 100 nA
tPG PG deglitch time for a high level to low level transition on the power good output 40 µs
OUTPUT
VFB Feedback voltage, adjustable version 0.6 V
VFB Feedback voltage, fixed voltage versions for TPS62850108 1.1 V
VFB Feedback voltage, fixed voltage versions for TPS6285018A 1.2 V
VFB Feedback voltage, fixed voltage versions for TPS6285010M, TPS6285020M 1.8 V
VFB Feedback voltage, fixed voltage versions for TPS6285021H 3.3 V
IFB,LKG Input leakage current into FB, adjustable version VFB = 0.6 V 1 70 nA
IFB,LKG Input leakage current into FB, fixed voltage versions 1 nA
VFB Feedback voltage accuracy PWM, VIN ≥ VOUT + 1 V -1 1 %
VFB Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.0 V, Co,eff ≥ 10 µF, L = 0.47µH -1 2 %
VFB Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT < 1.0 V, Co,eff ≥ 15 µF, L = 0.47µH
 		 -1 3 %
Load regulation PWM 0.05 %/A
Line regulation PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V 0.02 %/V
RDIS Output discharge resistance 100 Ω
fSW PWM Switching frequency range MODE = high, see the FSET pin functionality about setting the switching frequency 1.8 2.25 4 MHz
fSW PWM Switching frequency range MODE = low, see the FSET pin functionality about setting the switching frequency 1.8 3.5 MHz
fSW PWM Switching frequency with COMP/FSET tied to GND or VIN 2.025 2.25 2.475 MHz
fSW PWM Switching frequency tolerance using a resistor from COMP/FSET to GND -12 12 %
ton,min Minimum on-time of high-side FET VIN ≥ 3.3 V, TJ = -40°C to 125°C 35 50 ns
ton,min Minimum on-time of low-side FET 10 ns
RDS(ON) High-side FET on-resistance VIN ≥ 5 V
 		 65 120 mΩ
Low-side FET on-resistance VIN ≥ 5 V 33 70 mΩ
High-side MOSFET leakage current TJ = 85°C 2.5 µA
High-side MOSFET leakage current 0.01 44 µA
Low-side MOSFET leakage current TJ = 85°C 3.7 µA
Low-side MOSFET leakage current 0.01 70 µA
SW leakage V(SW) = 0.6V, current into SW pin -0.05 11 µA
ILIMH High-side FET switch current limit DC value, for TPS628503;
VIN = 3.3 V to 6		 3.45 4.5 5.1 A
ILIMH High-side FET switch current limit DC value, for TPS628502;
VIN = 3 V to 6 V		 2.85 3.4 3.9 A
ILIMH High-side FET switch current limit DC value, for TPS628501;
VIN = 3 V to 6 V		 2.1 2.6 3.0 A
ILIMNEG Low-side FET negative current limit DC value -1.8 A