SLUSDO4A August   2020  – March 2021 TPS628510 , TPS628511 , TPS628512

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Schematic
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable (EN)
      2. 9.3.2 MODE / SYNC
      3. 9.3.3 Spread Spectrum Clocking (SSC)
      4. 9.3.4 Undervoltage Lockout (UVLO)
      5. 9.3.5 Power Good Output (PG)
      6. 9.3.6 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short Circuit Protection
      5. 9.4.5 Foldback Current Limit and Short Circuit Protection
      6. 9.4.6 Output Discharge
      7. 9.4.7 Soft Start / Tracking (SS/TR)
      8. 9.4.8 Input Overvoltage Protection
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 Inductor Selection
      3. 10.1.3 Capacitor Selection
        1. 10.1.3.1 Input Capacitor
        2. 10.1.3.2 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Voltage Tracking
      2. 10.3.2 Synchronizing to an External Clock
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over operating junction remperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = VIN, no load, device not switching, MODE = GND, VOUT = 0.6 V 17 36 μA
ISD Shutdown current EN = GND, Nominal value at TJ = 25°C, Max value at TJ = 150°C 1.5 48 μA
VUVLO Undervoltage lockout threshold VIN rising 2.45 2.6 2.7 V
VIN falling 2.1 2.5 2.6 V
TJSD Thermal shutdown threshold TJ rising 170 °C
Thermal shutdown hysteresis TJ falling 15 °C
CONTROL and INTERFACE
VEN,IH Input threshold voltage at EN, rising edge 1.05 1.1 1.15 V
VEN,IL Input threshold voltage at EN, falling edge 0.96 1.0 1.05 V
VIH High-level input-threshold voltage at MODE/SYNC 1.1 V
IEN,LKG Input leakage current into EN VIH = VIN or VIL = GND 125 nA
VIL Low-level input-threshold voltage at MODE/SYNC 0.3 V
ILKG Input leakage current into MODE/SYNC 100 nA
tDelay Enable delay time Time from EN high to device starts switching; VIN applied already 85 150 470 µs
tRamp Output voltage ramp time Time from device starts switching to power good; device not in current limit 0.8 1.3 1.8 ms
tRamp Output voltage ramp time, SS/TR pin open Time from device starts switching to power good; device not in current limit 90 150 210 µs
ISS/TR SS/TR source current 2 2.5 2.8 uA
Tracking gain VFB / VSS/TR 1
Tracking offset VFB when VSS/TR = 0 V ±1 mV
fSYNC Frequency range on MODE/SYNC pin for synchronization 1.8 4 MHz
Duty cycle of synchronization signal at MODE/SYNC 20% 80%
Time to lock to external frequency 50 µs
VTH_PG UVP power good threshold voltage;
DC level
Rising (%VFB) 92% 95% 98%
VTH_PG UVP power good threshold voltage;
DC level
Falling (%VFB) 87% 90% 93%
VTH_PG OVP power good threshold voltage;
DC level
Rising (%VFB) 107% 110% 113%
OVP power good threshold voltage;
DC level
Falling (%VFB) 104% 107% 111%
VPG,OL Low-level output voltage at PG ISINK_PG = 2 mA 0.07 0.3 V
IPG,LKG Input leakage current into PG VPG = 5 V 100 nA
tPG PG deglitch time For a high level to low level transition on the power good output 40 µs
OUTPUT
VFB Feedback voltage, adjustable version 0.6 V
IFB,LKG Input leakage current into FB, adjustable version VFB = 0.6 V 1 70 nA
VFB Feedback voltage accuracy PWM, VIN ≥ VOUT + 1 V –1% 1%
VFB Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.0 V, Co,eff ≥ 10 µF, L = 0.47 µH –1% 2%
VFB Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT < 1.0 V, Co,eff ≥ 15 µF, L = 0.47 µH –1% 3%
VFB Feedback voltage accuracy with voltage tracking VIN ≥ VOUT + 1 V, VSS/TR = 0.3 V –4% 4%
Load regulation PWM 0.05 %/A
Line regulation PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V 0.02 %/V
RDIS Output discharge resistance 100 Ω
fSW PWM Switching frequency 2.025 2.25 2.475 MHz
ton,min Minimum on-time of high-side FET VIN = 3.3 V, TJ = –40°C to 125°C 35 52 ns
ton,min Minimum on-time of low-side FET 10 ns
RDS(ON) High-side FET on-resistance VIN ≥ 5 V 65 120
Low-side FET on-resistance VIN ≥ 5 V 33 70
High-side MOSFET leakage current 0.01 44 µA
Low-side MOSFET leakage current 0.01 70 µA
SW leakage V(SW) = 0.6 V, current into SW pin -0.05 11 µA
ILIMH High-side FET switch current limit DC value, for TPS628512;
VIN = 3 V to 6 V
2.85 3.4 3.9 A
ILIMH High-side FET switch current limit DC value, for TPS628511;
VIN = 3 V to 6 V
2.1 2.6 3.0 A
ILIMH High-side FET switch current limit DC value, for TPS628510;
VIN = 3 V to 6 V
1.6 2.1 2.5 A
ILIMNEG Low-side FET negative current limit DC value -1.8 A