SLUSDN8 March   2021 TPS62865 , TPS62867

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
      2. 8.3.2 Forced PWM Mode
      3. 8.3.3 100% Duty Cycle Mode Operation
      4. 8.3.4 Soft Start
      5. 8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Disable (EN)
      2. 8.4.2 Power Good (PG)
      3. 8.4.3 Voltage Setting and Mode Selection (VSET/MODE)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting The Output Voltage
        3. 9.2.2.3 Output Filter Design
        4. 9.2.2.4 Inductor Selection
        5. 9.2.2.5 Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

TJ = –40°C to 125°C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = High, no load, device not switching 4 10 µA
IQ_VOS Operating quiescent current into VOS pin EN = High, no load, device not switching, VVOS = 1.8 V 8 µA
ISD Shutdown current EN = Low, TJ = –40℃ to 85℃
 0.24 1 µA
VUVLO Undervoltage lockout threshold VIN rising 2.2 2.3 2.4 V
VIN falling 2.1 2.2 2.3 V
TJSD Thermal shutdown threshold TJ rising 150 °C
Thermal shutdown hysteresis TJ falling 20 °C
LOGIC INTERFACE
VIH High-level input threshold voltage at EN and VSET/MODE 0.84 V
VIL Low-level input threshold voltage at EN and VSET/MODE 0.4 V
IEN,LKG Input leakage current into EN pin 0.01 0.1 µA
STARTUP, POWER GOOD
tDelay Enable delay time Time from EN high to device starts switching
249-kΩ resistor connected between VSET/MODE and GND		 420 700 1100 µs
tRamp Output voltage ramp time Time from device starts switching to power good 0.8 1 1.5 ms
VPG Power good lower threshold VVOS referenced to VOUT nominal  85% 91% 96%
Power good upper threshold VVOS referenced to VOUT nominal  103% 111% 120%
VPG,OL Low-level output voltage Isink = 1 mA, PG pin version 0.36 V
tPG,DLY Power good deglitch delay Rising and falling edges 34 µs
OUTPUT
VOUT Output voltage accuracy Fixed voltage operation, FPWM, no load, TJ = 0°C to 85°C –1% 1%
Fixed voltage operation, FPWM, no load –2% 2%
VFB Feedback voltage Adjustable voltage operation 594 600 606 mV
IFB,LKG Input leakage into FB pin Adjustable voltage operation, VFB = 0.6 V 0.01 0.4 µA
IVOS,LKG Input leakage current into VOS pin Output discharge disabled, VVOS = 1.8 V 0.2 2.5 µA
RDIS Output discharge resistor at VOS pin 3.5 Ω
Load regulation VOUT = 0.9 V, FPWM  0.04 %/A
POWER SWITCH
RDS(on) High-side FET on-resistance 11 mΩ
Low-side FET on-resistance 10.5 mΩ
ILIM High-side FET forward current limit TPS62865 5 5.5 6 A
TPS62867 7 7.7 8.5 A
Low-side FET forward current limit TPS62865 4.5 A
TPS62867 6.5 A
Low-side FET negative current limit TPS62865, TPS62867 –3 A
fSW PWM switching frequency IOUT = 1 A, VOUT = 0.9 V 2.4 MHz