SLVSFS6A May   2021  – September 2021 TPS629210-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
      2. 8.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3 Settable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4 Smart Enable with Precise Threshold
      5. 8.3.5 Power Good (PG)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Current Limit and Short Circuit Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (PWM) Operation
      2. 8.4.2 AEE (Automatic Efficiency Enhancement)
      3. 8.4.3 Power Save Mode Operation (Auto PFM/PWM)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Output Discharge Function
      6. 8.4.6 Starting into a Pre-Biased Load
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection
        1. 9.1.1.1 Programming the Output Voltage
        2. 9.1.1.2 Inductor Selection
        3. 9.1.1.3 Capacitor Selection
          1. 9.1.1.3.1 Output Capacitor
          2. 9.1.1.3.2 Input Capacitor
        4. 9.1.1.4 Output Filter and Loop Stability
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Settable VO Operation (VSET and Internal Voltage Divider)

If the device is configured to VSET operation, the device interprets the VSET pin value following the MODE/S-CONF readout (see Figure 8-3). There is no further interpretation of the VSET pin during operation and the output voltage cannot be changed afterwards without toggling the EN pin.

Figure 8-3 shows the typical schematic for this configuration, where VO is directly sensed at the VOS terminal of the device. VO is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by an external resitor connected between VSET and GND (see Table 8-2).

GUID-B6BA8963-CA56-4615-B909-5AE56621E1E9-low.gif Figure 8-3 Settable VO Operation Schematic
Table 8-2 VSET Selection Table
VSET-# RESISTOR VALUE [Ω](1) TARGET VO [V]
1 GND 1.2
2 4.87 k 0.4
3 6.04 k 0.6
4 7.50 k 0.8
5 9.31 k 0.85
6 11.50 k 1.0
7 14.30 k 1.1
8 17.80 k 1.25
9 22.10 k 1.3
10 27.40 k 1.35
11 34.00 k 1.8
12 42.20 k 1.9
13 52.30 k 2.5
14 64.90 k 3.8
15 80.60 k 5.0
16 100.00 k 5.1
17 124.00 k 5.5
18 249.00 k or larger
/Open
3.3
E96 Resistor Series, 1% accuracy, temperature coefficient better or equal to ±200 ppm/°C