SLUSEA4D June   2021  – August 2022 TPS62932 , TPS62933 , TPS62933F , TPS62933O , TPS62933P

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Fixed Frequency Peak Current Mode
      2. 9.3.2  Pulse Frequency Modulation
      3. 9.3.3  Voltage Reference
      4. 9.3.4  Output Voltage Setting
      5. 9.3.5  Switching Frequency Selection
      6. 9.3.6  Enable and Adjusting Undervoltage Lockout
      7. 9.3.7  External Soft Start and Prebiased Soft Start
      8. 9.3.8  Power Good
      9. 9.3.9  Minimum On Time, Minimum Off Time, and Frequency Foldback
      10. 9.3.10 Frequency Spread Spectrum
      11. 9.3.11 Overvoltage Protection
      12. 9.3.12 Overcurrent and Undervoltage Protection
      13. 9.3.13 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Modes Overview
      2. 9.4.2 Heavy Load Operation
      3. 9.4.3 Light Load Operation
      4. 9.4.4 Out of Audio Operation
      5. 9.4.5 Forced Continuous Conduction Operation
      6. 9.4.6 Dropout Operation
      7. 9.4.7 Minimum On-Time Operation
      8. 9.4.8 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design With WEBENCH® Tools
        2. 10.2.2.2  Output Voltage Resistors Selection
        3. 10.2.2.3  Choosing Switching Frequency
        4. 10.2.2.4  Soft-Start Capacitor Selection
        5. 10.2.2.5  Bootstrap Capacitor Selection
        6. 10.2.2.6  Undervoltage Lockout Setpoint
        7. 10.2.2.7  Output Inductor Selection
        8. 10.2.2.8  Output Capacitor Selection
        9. 10.2.2.9  Input Capacitor Selection
        10. 10.2.2.10 Feedforward Capacitor CFF Selection
        11. 10.2.2.11 Maximum Ambient Temperature
      3. 10.2.3 Application Curves
    3. 10.3 What to Do and What Not to Do
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

Figure 7-1 TPS62932, TPS62933, and TPS62933F 8-Pin SOT583DRL Package(Top View)
Figure 7-2 TPS62933P and TPS62933O 8-Pin SOT583DRL Package(Top View)
Table 7-1 Pin Functions
Pin Type(1) Description
Name NO.
RT 1 A Frequency programming input. Float for 500 kHz, tie to GND for 1.2 MHz, or connect to an RT timing resistor. See Section 9.3.5 for details.
EN 2 A Enable input to the converter. Driving EN high or leaving this pin floating enables the converter. An external resistor divider can be used to implement an adjustable VIN UVLO function.
VIN 3 P Supply input pin to internal LDO and high-side FET. Input bypass capacitors must be directly connected to this pin and GND.
GND 4 G Ground pin. Connected to the source of the low-side FET as well as the ground pin for the controller circuit. Connect to system ground and the ground side of CIN and COUT. The path to CIN must be as short as possible.
SW 5 P Switching output of the convertor. Internally connected to the source of the high-side FET and drain of the low-side FET. Connect to the power inductor.
BST 6 P Bootstrap capacitor connection for high-side FET driver. Connect a high-quality, 100-nF ceramic capacitor from this pin to the SW pin.
SS/PG 7 A TPS62932, TPS62933, and TPS62933F soft-start control pin. An external capacitor connected to this pin sets the internal voltage reference rising time. See Section 9.3.7 for details. A minimum 6.8-nF ceramic capacitor must be connected at this pin, which sets the minimum soft-start time to approximately 1 ms. Do not float.
A TPS62933P and TPS62933O open-drain power good indicator, which is asserted low if output voltage is out of PG threshold, overvoltage, or if the device is under thermal shutdown, EN shutdown, or during soft start.
FB 8 A Output feedback input. Connect FB to the tap of an external resistor divider from the output to GND to set output voltage.
(1) A = Analog, P = Power, G = Ground