The TPS63805 and TPS63806 use a peak current mode control architecture. It has an inner current loop where it measures the peak current of the boost high-side MOSFET and compares it to a reference current. This current is the output of the outer voltage loop. It measures the output voltage via the FB-pin and compares it with the internal voltage reference. That means, the outer voltage loop measures the voltage error (VREF-VFB), and transforms it into the system current demand (IREF) for the inner current loop.
Figure 4 shows the simplified schematic of the control loop. The error amplifier and the type-2 compensation represent the voltage loop. The voltage output is converted into the reference current IREF and fed into the current comparator.
The scheme shows the skip-comparator handling the power-save mode (PFM) to achieve high efficiency at light loads. See Power Save Mode Operation for further details.