12.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TPS63805 and TPS63806 device.
- Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Route wide and direct traces to the input and output capacitor results in low trace resistance and low parasitic inductance.
- Separate AGND and PGND. Do not connect AGND and PGND directly at the IC. See Figure 69 as an example.
- Use a common-power GND, but connect AGND and PGND through a via at a different layer.
- Use separate traces for the supply voltage of the power stage and the supply voltage of the analog stage.
- The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes.