SLVSEW4 April   2019 TPS650002-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converter
      2. 7.3.2 Soft Start
      3. 7.3.3 Linear Regulators
      4. 7.3.4 Power Good
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor Selection
        2. 8.2.2.2 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over full operating ambient temperature range, typical values are at TA = 25° C. Unless otherwise noted, specifications apply for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING VOLTAGE
VIN Input voltage for VINDCDC of DC-DC converter 2.3 6 V
Input voltage for LDO1 (VINLDO1) See (1) 1.6 6 V
Input voltage for LDO2 (VINLDO2) See (1) 1.6 6 V
Internal undervoltage (UVLO) lockout threshold VCC falling 1.72 1.77 1.82 V
Internal undervoltage (UVLO) lockout hysteresis 160 mV
SUPPLY CURRENT
IQ Operating quiescent current MODE low, EN_DCDC high,
EN_LDO1, EN_LDO2 low,
IOUT = 0 mA and no switching		 23 32 μA
MODE low, EN_DCDC low,
EN_LDO1, EN_LDO2 high, IOUT = 0 mA
IOUT = 0 mA and no switching		 50 57
EN_DCDC high, MODE high,
EN_LDO1, EN_LDO2 low, IOUT = 0 mA 		4 mA
ISD Shutdown Current EN_DCDC low EN_LDO1 and EN_LDO2 low 0.16 2.2 μA
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG
VIH High-level input voltage 1.2 V
VIL Low-level input voltage 0.4 V
VOL Low-level output voltage PG pins only, IO = –100 μA 0.4 V
Ilkg Input leakage current MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to GND or VINDCDC, 0.01 0.1 μA
OSCILLATOR
fSW Oscillator frequency 2.01 2.25 2.41 MHz
STEP-DOWN CONVERTER POWER SWITCH
rDS(on) High-side MOSFET ON-resistance VINDCDC = VGS = 3.6 V 240 480 mΩ
Low-side MOSFET ON-resistance VINDCDC = VGS = 3.6 V 185 380 mΩ
IO DC output current 2.3 V ≤ VINDCDC ≤ 2.5 V 300 mA
2.5 V ≤ VINDCDC ≤ 6 V 600
ILIMF Forward current limit, PMOS and NMOS 2.3 V ≤ VINDCDC ≤ 6 V 800 1000 1400 mA
STEP-DOWN CONVERTER POWER SWITCH (continued)
TSD Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 30 °C
STEP-DOWN CONVERTER OUTPUT VOLTAGE
VDCDC Fixed output voltage, VDCDC 1.825 V
VDCDC Output-voltage DC accuracy (PWM mode)(2) MODE = high,
2.3 ≤ VINDCDC  ≤ 6 V		 -1.5% +1.5%
Output-voltage DC accuracy (PFM mode) MODE low
+1% voltage positioning active 		1%
Load regulation (PWM mode) MODE high 0.5 %/A
RDIS Internal discharge resistance at SW EN_DCDC low 450 Ω
LOW-DROPOUT REGULATORS
VI Input voltage for LDOx (VINLDOx) 1.6 6 V
VLDO1 Fixed output voltage, LDO1 (VLDO1)(3) 2.8 V
VLDO2 Fixed output voltage, LDO2 (VLDO2)(3) 1.2 V
IO Continuous-pass FET current 300 mA
ISC Short-circuit current limit 2.3 V ≤ VINLDOx 340 825 mA
VINLDOx < 2.3 V 210 825
VDO Dropout voltage (4) VINLDOx ≥ 2.3 V, IOUT = 250 mA 370 mV
VINLDOx < 2.3 V, IOUT = 175 mA 370 mV
Output voltage accuracy IO = 1 mA to 300 mA, VINLDOx = 2.3 V–6 V,
VLDOx = 1.2 V		 –3.5% 3.5%
IO = 1 mA to 175 mA, VINLDOx = 1.6 V–6 V,
VLDOx = 1.2 V		 –3.5% 3.5%
Load regulation IO = 1 mA to 300 mA, VINLDOx = 3.6 V
VLDOx = 1.2 V		 –1.5% 1.5%
Line regulation VINLDOx = 1.6 V–6 V, VLDOx = 1.2 V at
IO = 1 mA		 –0.5% 0.5%
PSRR Power-supply rejection ratio fNOISE ≤ 10 kHz, COUT ≥ 2.2 μF, VIN = 2.3 V,
VOUT = 1.3 V, IOUT = 10 mA		 40 dB
RDIS Internal discharge resistance at VLDOx EN_LDOx low 450 Ω
TSD Thermal shutdown Increasing temperature 150 °C
Thermal shutdown hysteresis Decreasing temperature 30 °C
(1) The design principle allows only VINDCDC to be the highest supply in the system. If separate input voltage supplies are used for the DC-DC converter and LDOs, then choose VINDCDC ≥ VINLDO1 and VINDCDC ≥ VINLDO2.
(2) For VINDCDC = VDCDC + 1 V
(3) Maximum output voltage VLDOx = 3.6 V.
(4) VDO = VINLDOx – VLDOx, where VINLDOx = VLDOx(nom) – 100 mV