SLVS843B December   2008  – May 2018 TPS650250

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Detailed Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Dissipation Ratings
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics VDCDC1
    8. 6.8  Electrical Characteristics VDCDC2
    9. 6.9  Electrical Characteristics VDCDC3
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converters, VDCDC1, VDCDC2 AND VDCDC3
      2. 7.3.2 Power Save Mode Operation
      3. 7.3.3 Soft Start
      4. 7.3.4 100% Duty Cycle Low Dropout Operation
      5. 7.3.5 Low Dropout Voltage Regulators
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 PWRFAIL
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Configuration For The Samsung Processor S3C6400-533MHz
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection for the DCDC Converters
        2. 8.2.3.2 Output Capacitor Selection
        3. 8.2.3.3 Input Capacitor Selection
        4. 8.2.3.4 Output Voltage Selection
        5. 8.2.3.5 Voltage Change on VDCDC3
        6. 8.2.3.6 Vdd_alive Output
        7. 8.2.3.7 LDO1 and LDO2
        8. 8.2.3.8 Vcc-Filter
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RHB Package
32-Pin VQFN With Exposed Thermal Pad
Top View
TPS650250 po_lvs843.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
SWITCHING REGULATOR SECTION
AGND1 31 — Analog ground connection. All analog ground pins are connected internally on the chip.
AGND2 13 — Analog ground connection. All analog ground pins are connected internally on the chip.
Thermal pad — — Connect the power pad to analog ground.
VINDCDC1 5 I Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3 and VCC.
L1 6 — Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
VDCDC1 8 I VDCDC1 feedback voltage sense input, connect directly to VDCDC1.
PGND1 7 — Power ground for VDCDC1 converter.
VINDCDC2 28 I Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3 and VCC.
L2 27 — Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
VDCDC2 25 I VDCDC2 feedback voltage sense input, connect directly to VDCDC2.
PGND2 26 — Power ground for VDCDC2 converter.
VINDCDC3 4 I Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2 and VCC.
L3 3 — Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
VDCDC3 1 I VDCDC3 feedback voltage sense input, connect directly to VDCDC3.
PGND3 2 — Power ground for VDCDC3 converter.
Vcc 29 I Power supply for digital and analog circuitry of DCDC1, DCDC2 and DCDC3 DC-DC converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1 and VINDCDC2.
DEFDCDC1 9 I Input signal indicating default VDCDC1 voltage, 0 = 2.8V, 1 = 3.3V .
This pin can also be connected to a resistor divider between VDCDC1 and GND. In this case the output voltage of the DCDC1 converter can be set in a range from 0.6V to VINDCDC1.
DEFDCDC2 22 I Input signal indicating default VDCDC2 voltage, 0 = 1.8V, 1 = 2.5V .
This pin can also be connected to a resistor divider between VDCDC2 and GND. In this case the output voltage of the DCDC2 converter can be set in a range from 0.6V to VINDCDC2.
DEFDCDC3 32 I This pin must be connected to a resistor divider between VDCDC3 and GND. The output voltage of the DCDC3 converter can be set in a range from 0.6V to VINDCDC3.
EN_DCDC1 20 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
EN_DCDC2 19 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
EN_DCDC3 18 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
LDO REGULATOR SECTION
VINLDO 15 I Input voltage for LDO1 and LDO2.
VLDO1 16 O Output voltage of LDO1.
VLDO2 14 O Output voltage of LDO2.
EN_LDO 17 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs.
EN_Vdd_alive 24 I Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO.
Vdd_alive 12 O Output voltage for Vdd_alive.
FB_LDO1 11 I Feedback pin for LDO1.
FB_LDO2 10 I Feedback pin for LDO2.
CONTROL AND I2C SECTION
MODE 23 I Select between Power Safe Mode and forced PWM Mode for DCDC1, DCDC2 and DCDC3. In Power Safe Mode PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then Device operates in Power Safe Mode.
PWRFAIL 21 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
PWRFAIL_SNS 30 I Input for the comparator driving the /PWRFAIL output.