SLVS493D MARCH   2004  – January 2016 TPS65130 , TPS65131

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Conversion
      2. 7.3.2 Control
      3. 7.3.3 Enable
      4. 7.3.4 Load Disconnect
      5. 7.3.5 Soft-Start
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 Undervoltage Lockout
      8. 7.3.8 Overtemperature Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Save Mode
      2. 7.4.2 Full Operation with VIN > 2.7 V
      3. 7.4.3 Limited Operation with VUVLO < VIN < 2.7 V
      4. 7.4.4 No Operation with VIN < VUVLO
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming the Output Voltage
          1. 8.2.2.1.1 Boost Converter
          2. 8.2.2.1.2 Inverting Converter
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Capacitor Selection
          1. 8.2.2.3.1 Input Capacitor
          2. 8.2.2.3.2 Output Capacitors
        4. 8.2.2.4 Rectifier Diode Selection
        5. 8.2.2.5 External PMOS Selection
        6. 8.2.2.6 Stabilizing the Control Loop
          1. 8.2.2.6.1 Feedforward Capacitor
          2. 8.2.2.6.2 Compensation Capacitors
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. Improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. Therefore, use wide and short traces for the main current paths and for the power ground tracks. The input capacitors (C1, C2, C3), output capacitors (C4, C5), the inductors (L1, L2), and the rectifying diodes (D1, D2) should be placed as close as possible to the IC to keep parasitic inductances low. Use a wide power ground (PGND) plane. Connect the analog ground pin (AGND) to the PGND plane. Further, connect the PGND plane with the exposed thermal pad. Place the feedback dividers as close as possible to the control pin (boost converter) or the VREF pin (inverting converter) of the IC.

10.2 Layout Example

TPS65130 TPS65131 Layout.gif Figure 54. TPS6513x Layout Recommendation

10.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues, such as thermal coupling, airflow, added heatsinks and convection surfaces, and the presence of heat-generating components affect the power-dissipation limits of a given component.

The following are three basic approaches for enhancing thermal performance follow:

  • Improving the power dissipation capability of the PCB design.
  • Improving the thermal coupling of the component to the PCB.
  • Introducing airflow to the system.

The recommended device junction temperature range, TJ, is –40°C to 125°C. The thermal resistance of the 24-pin QFN, 4–mm × 4–mm package (RGE) is RθJA = 34.1°C/W. The recommended operating ambient temperature range for the device is TA = –40°C to 85°C. Use Equation 13 to calculate the maximum power dissipation, PDmax, as a function of TA. In this equation, use TJ = 125°C to operate the device within the recommended temperature range, use TJ = TTS to determine the absolute maximum threshold when the device might go into thermal shutdown. If the maximum ambient temperature of the application is lower, more heat dissipation is possible.

Equation 13. TPS65130 TPS65131 SLVSBB2D_equ13.gif