SLDS187A October   2018  – December 2019 TPS65216

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified Schematic
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Functions
      1.      Pin Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 5.3.1.1  Power-Up Sequencing
        2. 5.3.1.2  Power-Down Sequencing
        3. 5.3.1.3  Strobe 1 and Strobe 2
        4. 5.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 5.3.1.5  Internal LDO (INT_LDO)
        6. 5.3.1.6  Current Limited Load Switch
        7. 5.3.1.7  LDO1
        8. 5.3.1.8  UVLO
        9. 5.3.1.9  Power-Fail Comparator
        10. 5.3.1.10 DCDC3 and DCDC4 Power-Up Default Selection
        11. 5.3.1.11 I/O Configuration
          1. 5.3.1.11.1 Using GPIO2 as Reset Signal to DCDC1 and DCDC2
        12. 5.3.1.12 Push Button Input (PB)
          1. 5.3.1.12.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 5.3.1.12.2 Push Button Reset
        13. 5.3.1.13 AC_DET Input (AC_DET)
        14. 5.3.1.14 Interrupt Pin (INT)
        15. 5.3.1.15 I2C Bus Operation
    4. 5.4 Device Functional Modes
      1. 5.4.1 Modes of Operation
      2. 5.4.2 OFF
      3. 5.4.3 ACTIVE
      4. 5.4.4 SUSPEND
      5. 5.4.5 RESET
    5. 5.5 Register Maps
      1. 5.5.1 Password Protection
      2. 5.5.2 FLAG Register
      3. 5.5.3 TPS65216 Registers
        1. 5.5.3.1  CHIPID Register (subaddress = 0x00) [reset = 0x05]
          1. Table 5-7 CHIPID Register Field Descriptions
        2. 5.5.3.2  INT1 Register (subaddress = 0x01) [reset = 0x00]
          1. Table 5-8 INT1 Register Field Descriptions
        3. 5.5.3.3  INT2 Register (subaddress = 0x02) [reset = 0x00]
          1. Table 5-9 INT2 Register Field Descriptions
        4. 5.5.3.4  INT_MASK1 Register (subaddress = 0x03) [reset = 0x00]
          1. Table 5-10 INT_MASK1 Register Field Descriptions
        5. 5.5.3.5  INT_MASK2 Register (subaddress = 0x04) [reset = 0x00]
          1. Table 5-11 INT_MASK2 Register Field Descriptions
        6. 5.5.3.6  STATUS Register (subaddress = 0x05) [reset = 00XXXXXXb]
          1. Table 5-12 STATUS Register Field Descriptions
        7. 5.5.3.7  CONTROL Register (subaddress = 0x06) [reset = 0x00]
          1. Table 5-13 CONTROL Register Field Descriptions
        8. 5.5.3.8  FLAG Register (subaddress = 0x07) [reset = 0x00]
          1. Table 5-14 FLAG Register Field Descriptions
        9. 5.5.3.9  PASSWORD Register (subaddress = 0x10) [reset = 0x00]
          1. Table 5-15 PASSWORD Register Field Descriptions
        10. 5.5.3.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x00]
          1. Table 5-16 ENABLE1 Register Field Descriptions
        11. 5.5.3.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x00]
          1. Table 5-17 ENABLE2 Register Field Descriptions
        12. 5.5.3.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]
          1. Table 5-18 CONFIG1 Register Field Descriptions
        13. 5.5.3.13 CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]
          1. Table 5-19 CONFIG2 Register Field Descriptions
        14. 5.5.3.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
          1. Table 5-20 CONFIG3 Register Field Descriptions
        15. 5.5.3.15 DCDC1 Register (offset = 0x16) [reset = 0x99]
          1. Table 5-21 DCDC1 Register Field Descriptions
        16. 5.5.3.16 DCDC2 Register (subaddress = 0x17) [reset = 0x99]
          1. Table 5-22 DCDC2 Register Field Descriptions
        17. 5.5.3.17 DCDC3 Register (subaddress = 0x18) [reset = 0x8C]
          1. Table 5-23 DCDC3 Register Field Descriptions
        18. 5.5.3.18 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]
          1. Table 5-24 DCDC4 Register Field Descriptions
        19. 5.5.3.19 SLEW Register (subaddress = 0x1A) [reset = 0x06]
          1. Table 5-25 SLEW Register Field Descriptions
        20. 5.5.3.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
          1. Table 5-26 LDO1 Register Field Descriptions
        21. 5.5.3.21 SEQ1 Register (subaddress = 0x20) [reset = 0x00]
          1. Table 5-27 SEQ1 Register Field Descriptions
        22. 5.5.3.22 SEQ2 Register (subaddress = 0x21) [reset = 0x00]
          1. Table 5-28 SEQ2 Register Field Descriptions
        23. 5.5.3.23 SEQ3 Register (subaddress = 0x22) [reset = 0x98]
          1. Table 5-29 SEQ3 Register Field Descriptions
        24. 5.5.3.24 SEQ4 Register (subaddress = 0x23) [reset = 0x75]
          1. Table 5-30 SEQ4 Register Field Descriptions
        25. 5.5.3.25 SEQ5 Register (subaddress = 0x24) [reset = 0x12]
          1. Table 5-31 SEQ5 Register Field Descriptions
        26. 5.5.3.26 SEQ6 Register (subaddress = 0x25) [reset = 0x63]
          1. Table 5-32 SEQ6 Register Field Descriptions
        27. 5.5.3.27 SEQ7 Register (subaddress = 0x26) [reset = 0x03]
          1. Table 5-33 SEQ7 Register Field Descriptions
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Output Filter Design
        2. 6.2.2.2 Inductor Selection for Buck Converters
        3. 6.2.2.3 Output Capacitor Selection
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information
      2. 10.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENTS
VIN_BIAS Input supply voltage range Normal operation 3.6 5.5 V
EEPROM programming 4.5 5.5
Deglitch time 5 ms
IOFF OFF state current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LS VIN = 3.6 V; All rails disabled.
TJ = 0°C to 85°C 		5 µA
ISUSPEND SUSPEND current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LS VIN = 3.6 V; DCDC3 enabled, low-power mode, no load.
All other rails disabled.
TJ = 0°C to 105°C 		220 µA
INT_LDO
VINT_LDO Output voltage 2.5 V
DC accuracy IOUT < 10 mA –2% 2%
IOUT Output current range Maximum allowable external load 0 10 mA
ILIMIT Short circuit current limit Output shorted to GND 23 mA
tHOLD Hold-up time Measured from VINT_LDO = to VINT_LDO = 1.8 V
All rails enabled before power off,
VIN_BIAS = 2.8 V to 0 V in < 5 µs
No external load on INT_LDO
CINT_LDO = 1 µF, see Table 6-3.		 150 ms
COUT Nominal output capacitor value Ceramic, X5R or X7R, see Table 6-3. 0.1 1 22 µF
Tolerance Ceramic, X5R or X7R, rated voltage ≥ 6.3 V –20% 20%
DCDC1 (1.1-V BUCK)
VIN_DCDC1 Input voltage range VIN_BIAS > VUVLO 3.6 5.5 V
VDCDC1 Output voltage range Adjustable through I2C 0.85 1.675 V
DC accuracy 3.6 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A –2% 2%
Dynamic accuracy In respect to nominal output voltage
IOUT = 50 mA to 450 mA in < 1 µs
COUT ≥ 10 µF, over full input voltage range.		 –2.5% 2.5%
IOUT Continuous output current VIN_DCDC1 > 3.6 V 1.8 A
IQ Quiescent current Total current from IN_DCDC1 pin; Device not switching, no load 25 50 µA
RDS(ON) High-side FET on resistance VIN_DCDC1 = 3.6 V 230 355 mΩ
Low-side FET on resistance VIN_DCDC1 = 3.6 V 90 145
ILIMIT High-side current limit VIN_DCDC1 = 3.6 V 2.8 A
Low-side current limit VIN_DCDC1 = 3.6 V 3.1
VPG Power-good threshold VOUT falling STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 96% 96.5% 97%
Hysteresis VOUT rising STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 103% 103.5% 104%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC1 = 3.6 V; COUT = 10 µF to 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
L Nominal inductor value See Table 6-2. 1 1.5 2.2 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3. 10 22 100(5) µF
DCDC2 (1.1-V BUCK)
VIN_DCDC2 Input voltage range VIN_BIAS > VUVLO 3.6 5.5 V
VDCDC2 Output voltage range Adjustable through I2C 0.85 1.675 V
DC accuracy 3.6 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A –2% 2%
Dynamic accuracy In respect to nominal output voltage
IOUT = 50 mA to 450 mA in < 1 µs
COUT ≥ 10 µF, over full input voltage range		 –2.5% 2.5%
IOUT Continuous output current VIN_DCDC2 > 3.6 V 1.8 A
IQ Quiescent current Total current from IN_DCDC2 pin; device not switching, no load 25 50 µA
RDS(ON) High-side FET on resistance VIN_DCDC2 = 3.6 V 230 355 mΩ
Low-side FET on resistance VIN_DCDC2 = 3.6 V 90 145
ILIMIT High-side current limit VIN_DCDC2 = 3.6 V 2.8 A
Low-side current limit VIN_DCDC2 = 3.6 V 3.1
VPG Power-good threshold VOUT falling STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 96% 96.5% 97%
Hysteresis VOUT rising STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out Occurs at enable of DCDC2 and after DCDC2 register write (register 0x17). 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 103% 103.5% 104%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC2 = 3.6 V; COUT = 10 µF to 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
L Nominal inductor value See Table 6-2. 1 1.5 2.2 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3. 10 22 100(5) µF
DCDC3 (1.2-V BUCK)
VIN_DCDC3 Input voltage range VIN_BIAS > VUVLO 3.6 5.5 V
VDCDC3 Output voltage range Adjustable through I2C 0.9 3.4 V
DC accuracy 3.6 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A,
VIN_DCDC3 ≥ (VDCDC3 + 700 mV)		 –2% 2%
Dynamic accuracy In respect to nominal output voltage
IOUT = 50 mA to 450 mA in < 1 µs
COUT ≥ 10 µF, over full input voltage range		 –2.5% –2.5%
IOUT Continuous output current VIN_DCDC3 > 3.6 V 1.8 A
IQ Quiescent current Total current from IN_DCDC3 pin;
Device not switching, no load		 25 50 µA
RDS(ON) High-side FET on resistance VIN_DCDC3 = 3.6 V 230 345 mΩ
Low-side FET on resistance VIN_DCDC3 = 3.6 V 100 150
ILIMIT High-side current limit VIN_DCDC3 = 3.6 V 2.8 A
Low-side current limit VIN_DCDC3 = 3.6 V 3
VPG Power-good threshold VOUT falling STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 95% 95.5% 96%
Hysteresis VOUT rising STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out Occurs at enable of DCDC3 and after DCDC3 register write (register 0x18). 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 104% 104.5% 105%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC3 = 3.6 V; COUT = 10 µF to 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
L Nominal inductor value See Table 6-2. 1.0 1.5 2.2 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3. 10 22 100 µF
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O
VIN_DCDC4 Input voltage operating range VIN_BIAS > VUVLO, –40°C to +105°C 3.6 5.5 V
VDCDC4 Output voltage range Adjustable through I2C 1.175 3.3 V
VDCDC4 DC accuracy 4.2 V ≤ VIN ≤ 5.5 V;
3 V < VOUT ≤ 3.4 V
0 A ≤ IOUT ≤ 1.6 A 		–2% 2%
3.3 V ≤ VIN ≤ 4.2 V;
3 V < VOUT ≤ 3.4 V
0 A ≤ IOUT ≤ 1.3 A		 –2% 2%
2.8 V ≤ VIN ≤ 5.5 V;
1.65 V < VOUT ≤ 3 V
0 A ≤ IOUT ≤ 1 A		 –2% 2%
2.8 V ≤ VIN ≤ 5.5 V;
1.175 V < VOUT ≤ 1.65 V
0 A ≤ IOUT ≤ 1 A		 –2.5% 2.5%
Output voltage ripple PFM mode enabled;
4.2 V ≤ VIN ≤ 5.5 V;
0 A ≤ IOUT ≤
VOUT = 3.3 V		 mVpp
Minimum duty cycle in step-down mode 18%
IOUT Continuous output current VIN_DCDC4 = 2.8 V, VOUT = 3.3 V 1 A
VIN_DCDC4 = 3.6 V, VOUT = 3.3 V 1.3
VIN_DCDC4 = 5 V, VOUT = 3.3 V 1.6
IQ Quiescent current Total current from IN_DCDC4 pin; Device not switching, no load. 25 50 µA
fSW Switching frequency 2400 kHz
RDS(ON) High-side FET on resistance VIN_DCDC3 = 3.6 V IN_DCDC4 to L4A 166 mΩ
L4B to DCDC4 149
Low-side FET on resistance VIN_DCDC3 = 3.6 V L4A to GND 142 190
L4B to GND 144 190
ILIMIT Average switch current limit VIN_DCDC4 = 3.6 V 3000 mA
VPG Power-good threshold VOUT falling STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 95% 95.5% 96%
Hysteresis VOUT rising STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out Occurs at enable of DCDC4 and after DCDC4 register write (register 0x19) 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 104% 104.5% 105%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC4 = 3.6 V ≤ VINDCDC4 ≤ 5.5 V; 40 µF ≤ COUT ≤ 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
L Nominal inductor value See Table 6-2. 1.2 1.5 2.2 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3. 40 80 100 µF
LDO1 (1.8-V LDO)
VIN_LDO1 Input voltage range VIN_BIAS > VUVLO 1.8 5.5 V
IQ Quiescent current No load 35 µA
VOUT Output voltage range Adjustable through I2C 0.9 3.4 V
DC accuracy VOUT + 0.2 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 200 mA –2% 2%
IOUT Output current range VIN_LDO1 – VDO = VOUT 0 200 mA
VIN_LDO1 > 2.7 V, VOUT = 1.8 V 0 400
ILIMIT Short circuit current limit Output shorted to GND 445 550 mA
VDO Dropout voltage IOUT = 100 mA, VIN = 3.6 V 200 mV
VPG Power-good threshold VOUT falling STRICT = 0b 86% 90% 94%
STRICT = 1b 95% 95.5% 96%
Hysteresis, VOUT rising STRICT = 0b 3% 4% 5%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 104% 104.5% 105%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
VOUT falling, STRICT = 1b 1 ms
RDIS Discharge resistor 150 250 380 Ω
COUT Output capacitance value Ceramic, X5R or X7R 22 100 µF
LOAD SWITCH
VIN_LS Input voltage range VIN_BIAS > VUVLO 1.8 10 V
RDS(ON) Static on resistance VIN_LS = 9 V, IOUT= 500 mA, over full temperature range 440 mΩ
VIN_LS = 5 V, IOUT= 500 mA, over full temperature range 526
VIN_LS = 2.8 V, IOUT= 200 mA, over full temperature range 656
VIN_LS = 1.8 V, IOUT= 200 mA, over full temperature range 910
ILIMIT Short circuit current limit VIN_LS > 2.3 V,
Output shorted to GND		 LSILIM[1:0] = 00b 98 126 mA
LSILIM[1:0] = 01b 194 253
LSILIM[1:0] = 10b 475 738
LSILIM[1:0] = 11b 900 1234
VIN_LS ≤ 2.3 V,
Output shorted to GND 		LSILIM[1:0] = 00b 98 126
LSILIM[1:0] = 01b 194 253
LSILIM[1:0] = 10b 475 738
tBLANK Interrupt blanking time Output shorted to GND until interrupt is triggered. 15 ms
RDIS Internal discharge resistor at output(1) LSDCHRG = 1 650 1000 1500 Ω
TOTS Overtemperature shutdown(2) 125 132 139 °C
Hysteresis 10 °C
COUT Nominal output capacitance value Ceramic, X5R or X7R, see Table 6-3. 1 100 220 µF
I/O LEVELS AND TIMING CHARACTERISTICS
PGDLY PGOOD delay time PGDLY[1:0] = 00b 10 ms
PGDLY[1:0] = 01b 20
PGDLY[1:0] = 10b 50
PGDLY[1:0] = 11b 150
tDG Deglitch time PB input Rising edge 100 ms
Falling edge 50 ms
AC_DET input Rising edge 100 µs
Falling edge 10 ms
PWR_EN input Rising edge 10 ms
Falling edge 100 µs
GPIO1 Rising edge 1 ms
Falling edge 1 ms
GPIO2 Rising edge 5 µs
Falling edge 5 µs
tRESET Reset time PB input held low TRST = 0b 8 s
TRST = 1b 15
VIH High level input voltage SCL, SDA, GPIO1, and GPIO2 1.3 V
AC_DET, PB 0.66 × IN_BIAS
PWR_EN 1.3
VIL Low level input voltage SCL, SDA, PWR_EN, AC_DET, PB, GPIO1, and GPIO2 0 0.4 V
VOL Low level output voltage nWAKEUP, nINT, SDA, PGOOD, GPIO1, and GPIO2; ISINK = 2 mA 0 0.3 V
nPFO; ISINK = 2 mA 0 0.35
VPFI Power-fail comparator threshold Input falling 800 mV
Hysteresis Input rising 40 mV
Accuracy –4% 4%
Deglitch Input falling 25 µs
Input rising 10 ms
IDC34_SEL DC34_SEL bias current Enabled only at power-up. 10 µA
VDC34_SEL DCDC3 and DCDC4 power-up default selection thresholds Threshold 1 100 mV
Threshold 2 163
Threshold 3 275
Threshold 4 400
Threshold 5 575
Threshold 6 825
Threshold 7 1200
RDC34_SEL DCDC3 and DCDC4 power-up default selection resistor values Setting 0 0 0 7.7 kΩ
Setting 1 12.1
Setting 2 20
Setting 3 30.9 31.6 32.3
Setting 4 45.3
Setting 5
Setting 6 95.3
Setting 7 150
IBIAS Input bias current SCL, SDA, GPIO1(3), GPIO2(3); VIN = 3.3 V 0.01 1 µA
PB, AC_DET, PFI; VIN = 3.3 V 500 nA
ILEAK Pin leakage current nINT, nWAKEUP, nPFO, PGOOD, PWR_EN, GPIO1(4), GPIO2(4)
VOUT = 3.3 V 		500 nA
OSCILLATOR
ƒOSC Oscillator frequency 2400 kHz
Frequency accuracy TJ = –40°C to +105°C –12% 12%
OVERTEMPERATURE SHUTDOWN
TOTS Overtemperature shutdown Increasing junction temperature 135 145 155 °C
Hysteresis Decreasing junction temperature 20
TWARN High-temperature warning Increasing junction temperature 90 100 110 °C
Hysteresis Decreasing junction temperature 15
(1) Discharge function disabled by default.
(2) Switch is temporarily turned OFF if input voltage drops below UVLO threshold.
(3) Configured as input.
(4) Configured as output.
(5) 500-µF of remote capacitance can be supported for DCDC1 and DCDC2.