SLDS187A October 2018 – December 2019 TPS65216
By default, the power-down sequence follows the reverse of the power-up sequence. When the power-down sequence is triggered, STROBE 10 occurs and any rail assigned to STROBE 10 is shut down and its discharge circuit is enabled. After a delay time of DLY9, STROBE 9 occurs and any rail assigned to it is shut down and its discharge circuit is enabled. The sequence continues until all strobes occur and all DLYx times execute. The DLYx times are extended by a factor of 10x to provide ample time for discharge, and preventing output voltages from crossing during shut-down. The DLYFCTR bit is applied globally to all power-down delay times. Regardless of the DLYx and DLYFCTR settings, the PMIC enters OFF, SUSPEND, or RECOVERY state 500 ms after the power-down sequence initiates, to ensure that the discharge circuits remain enabled for a minimum of 150 ms before the next power-up sequence starts.
A power-down sequence executes if one of the following events occurs:
When transitioning from ACTIVE to SUSPEND state, the rails not controlled by the power-down sequencer maintains the same ON/OFF state in SUSPEND state that it had in ACTIVE state. This allows for the selected power rails to remain powered up when in the SUSPEND state.
When transitioning to the OFF or RECOVERY state, rails not under sequencer control are shut-down as follows:
If the supply voltage on IN_BIAS drops below 2.5 V, the digital core is reset and all power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4, and LDO1). The amount of time the discharge circuitry remains active is a function of the INT_LDO hold up time (see Section 126.96.36.199 for more details).