SLDS187A October 2018 – December 2019 TPS65216
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Slew-rate control applies to DCDC1 and DCDC2 only. If changing from a higher voltage to lower voltage while STRICT = 1 and converters are in a no load state, PFM bit for DCDC1 and DCDC2 must be set to 0.
Go bit. Note: Bit is automatically reset at the end of the voltage transition.
0b = No change
1b = Initiates the transition from present state to the output voltage setting currently stored in DCDC1 and DCDC2 register. SLEW setting does apply.
Go disable bit
0b = Enabled
1b = Disabled; DCDC1 and DCDC2 output voltage changes whenever set-point is updated in DCDC1 and DCDC2 register without having to write to the GO bit. SLEW setting does apply.
Output slew rate setting:
0h = 160 µs/step (0.0625 mV/µs at 10 mV per step)
1h = 80 µs/step (0.125 mV/µs at 10 mV per step)
2h = 40 µs/step (0.250 mV/µs at 10 mV per step)
3h = 20 µs/step (0.500 mV/µs at 10 mV per step)
4h = 10 µs/step (1.0 mV/µs at 10 mV per step)
5h = 5 µs/step (2.0 mV/µs at 10 mV per step)
6h = 2.5 µs/step (4.0 mV/µs at 10 mV per step)
7h = Immediate; slew rate is only limited by control loop response time. Note: The actual slew rate depends on the voltage step per code. Refer to DCDCx registers for details.