SLDS187A October 2018 – December 2019 TPS65216
The GPIO2 is an edge-sensitive reset input to the PMIC, when the DC12_RST bit set to 1. The reset signal affects DCDC1 and DCDC2 only, so that only those two registers are reset to the power-up default whenever GPIO2 input transitions from high to low, while all other registers maintain their current values. DCDC1 and DCDC2 transition back to the default value following the SLEW settings, and are not power cycled. This function recovers the processor from reset events while in low-power mode.