SLDS234B December 2017 – September 2018 TPS65218D0
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
With the DC12_RST bit set to 1, GPIO3 is an edge-sensitive reset input to the PMIC. The reset signal affects DCDC1 and DCDC2 only, so that only those two registers are reset to the power-up default whenever GPIO3 input transitions from high to low, while all other registers maintain their current values. DCDC1 and DCDC2 transition back to the default value following the SLEW settings, and are not power cycled. This function recovers the processor from reset events while in low-power mode.
GPIO must be configured as input (IO1_SEL = 1b). GPO2 is automatically configured as output.