8.3.1 Buck Controller (BUCK1)

The main buck controller operates using constant frequency peak current mode control. The output voltage is programmable with external resistors.

The switching frequency is set to a fixed value of f_SWBUCK1. Peak current-mode control regulates the peak current through the inductor such that the output voltage VBUCK1 is maintained to its set value. Current mode control allows superior line-transient response. The error between the feedback voltage VSENSE1 and the internal reference produces an error signal at the output of the error amplifier (COMP1) which serves as target for the peak inductor current. At S1–S2, the current through the inductor is sensed as a differential voltage and compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at VSENSE1, which causes COMP1 to rise or fall respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. In this way the output voltage VBUCK1 is maintained in regulation.

Figure 16. Detailed Block Diagram of Buck 1 Controller

The high-side N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the inductor current reaches its peak value as set by the voltage loop. Once the high external FET is turned OFF, and after a small delay (shoot-through delay), the lower N-channel MOSFET is turned on until the start of the next clock cycle. In dropout operation the high-side MOSFET stays on 100%. In every fourth period the duty cycle is limited to 95% in order to charge the bootstrap capacitor at BOOT1. This allows a maximum duty cycle of 98.75%.

The maximum value of COMP1 is clamped so that the maximum current through the inductor is limited to a specified value. The BUCK1 controller output voltage is monitored by a central independent voltage-monitoring circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In addition, BUCK1 is thermally protected with a dedicated temperature sensor.

8.3.2 Synchronous Buck Converters BUCK2 and BUCK3

Both regulators are synchronous converters operating with a fixed switching frequency ƒ_sw = 2.45 MHz. For each buck converter, the output voltage is programmable with external resistors. The synchronous operation mode improves the overall efficiency. BUCK3 switches in phase with BUCK1, and BUCK2 switches at a 216-degree shift to BUCK3 to minimize input current ripple.

Each buck converter can provide a maximum current of 2 A and is protected against short circuits to ground. In case of a short circuit to ground, the integrated cycle-by-cycle current limit turns off the high-side FET when its current reaches I_HS-Limit and the low-side FET is turned on until the end of the given cycle. When the current limit is reached in the beginning of the cycle for five consecutive cycles, the pulse-width modulation (PWM) is forced low for sixteen cycles to prevent uncontrolled current build-up. In case the low-side current limit of I_LS-Limit is reached, for example, because of an output short to the VSUP2 and VSUP23 pins, the low-side FET is turned off until the end of the cycle. If this is detected shortly after the high-low PWM transition (immediately after the low-side overcurrent comparator blanking time), both FETs are turned off for sixteen cycles.

The output voltages of the BUCK2 and BUCK3 regulators are monitored by a central independent voltage-monitoring circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In addition BUCK2 and BUCK3 are thermally protected with a dedicated temperature sensor.

8.3.3 BOOST Converter

The BOOST converter is an asynchronous converter operating with a fixed switching frequency ƒ_sw = 2.45 MHz. It switches in phase with BUCK1. At low load, the boost regulator switches to pulse skipping.

The output voltage is programmable with external resistors.

The internal low-side switch can handle maximum 1-A current, and is protected with a current limit. In case of an overcurrent, the integrated cycle-by-cycle current limit turns off the low-side FET when its current reaches I_CLBOOST until the end of the given cycle. When the current limit is reached in the beginning of the cycle for five consecutive cycles, the PWM is forced low for sixteen cycles to prevent uncontrolled current build-up.

The BOOST converter output voltage is monitored by a central independent voltage-monitoring circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. If the V_{MONTH_L} > V_SENSE5 or V_SENSE5 > V_{MONTH_H}, the output is switched off and the BOOST_FAIL bit in the SPI PWR_STAT register is set. The BOOST can be reactivated by setting BOOST_EN bit in the PWR_CONFIG register.

In addition, the BOOST converter is thermally protected with a dedicated temperature sensor. If T_J > T_OTTH, the BOOST converter is switched off and bit OT_BOOST in PWR_STAT register is set. Reactivation of the booster is only possible if the OT_BOOST bit is 0, and the booster enable bit in the PWR_CONFIG register is set to 1.

8.3.4 Frequency-Hopping Spread Spectrum

The TPS65311-Q1 features a frequency-hopping pseudo-random spectrum or triangular spreading architecture. The pseudo-random implementation uses a linear feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift register is designed in such a way that the frequency shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies. The triangular function uses an up-down counter. Whenever spread spectrum is enabled (SPI command), the internal oscillator frequency is varied from one BUCK1 cycle to the next within a band of 0.8 x f_OSC ... f_OSC from a total of 16 different frequencies. This means that BUCK3 and BOOST also step through 16 frequencies. The internal oscillator can also change its frequency during the period of BUCK2, yielding a total of 31 frequencies for BUCK2.

8.3.5 Linear Regulator LDO

The LDO is a low drop out regulator with an adjustable output voltage through an external resistive divider network. The output has an internal current-limit protection in case of an output overload or short circuit to ground. In addition, the output is protected against overtemperature. If T_J > T_OTTH, the LDO is switched off and bit OT_LDO in PWR_STAT register is set. Reactivation of the LDO is only possible through the SPI by setting the LDO enable bit in the PWR_CONFIG register to 1 if the OT_LDO bit is 0.

The LDO output voltage is monitored by a central independent voltage-monitoring circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. If the V_{MONTH_L} > V_SENSE4 or V_SENSE4 > V_{MONTH_H}, the output is switched off and the LDO_FAIL bit in the SPI PWR_STAT register is set. The LDO can be reactivated through the SPI by setting the LDO_EN bit in the PWR_CONFIG register. In case of overvoltage in VTCHECK and RAMP mode, the GPFET is turned off and the device changes to ERROR mode.

8.3.6 Gate Driver Supply

The gate drivers of the BUCK1 controller, BUCK2 and BUCK3 converters and the BOOST converter are supplied from an internal linear regulator. The internal linear regulator output (5.8-V typical) is available at the VREG pin and must be decoupled using a typical 2.2-μF ceramic capacitor. This pin has an internal current-limit protection and must not be used to power any other circuits.

The VREG linear regulator is powered from VINPROT by default when the EXTSUP voltage is less than 4.6 V (typical).

If the VINPROT is expected to go to high levels, there can be excessive power dissipation in this regulator when using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin, which can be connected to a supply less than VINPROT but high enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.8 V, the linear regulator automatically switches to EXTSUP as its input to provide this advantage. This automatic switch-over to EXTSUP can only happen once the TPS65311-Q1 device reaches ACTIVE mode. Efficiency improvements are possible when one of the switching regulator rails from the TPS65311-Q1, or any other voltage available in the system is used to power EXTSUP. The maximum voltage that must be applied to EXTSUP is 12 V.

8.3.7 RESET

RESN and PRESN are open drain outputs which are active if one or more of the conditions listed in Table 1 are valid. RESN active (low) is extended for t_RESNHOLD after a reset is triggered. RESN is the main processor reset and also asserts PRESN as a slave signal.

PRESN is latched and is released when window trigger mode of the watchdog is enabled (first rising edge at the WD pin).

RESN and PRESN must keep the main processor and peripheral devices in a defined state during power up and power down in case of improper supply voltages or a critical failure condition. Therefore, for low supply voltages the topology of the reset outputs specify that RESN and PRESN are always held at a low level when RESN and PRESN are asserted, even if V_IN falls below V_POR or the device is in SHUTDOWN mode.

Figure 17. RESET Functionality

Any reset event (without POR, thermal shutdown, or loss of LPM clock) increments the error counter (EC) by one. After a reset is consecutively triggered N_RES times, the device transfers to the LPM0 state, and the EC is reset to 0. The counter is decremented by one if an SPI LPM0_CMD is received. Alternatively, the device can be put in LOCK state once an SPI LOCK_CMD is received. Once the device is locked, it cannot be activated again by a wake condition. The reset counter and lock function avoid cyclic start-up and shut-down of the device in case of a persistent fault condition. The reset counter content is cleared with a POR condition, a thermal shutdown or a loss of LPM clock. Once the device is locked, a voltage below V_POR at VIN pin or a thermal shutdown condition are the only ways to unlock the device.

8.3.8 Soft Start

The output voltage slopes of BUCK, BOOST and LDO regulators are limited during ramp-up (defined by t_STARTx). During this period the target output voltage slowly settles to its final value, starting from 0 V. In consequence, regulators that offer low-side transistors (BUCK1, BUCK2 and BUCK3) actively discharge their output rails to the momentary ramp-value if previously charged to a higher value.

8.3.9 Power-on Reset Flag

The POR flag in the SYS_STAT SPI register is set:

• When V_IN is below the V_POR threshold
• System is in thermal shutdown
• Over or undervoltage on DVDD
• Loss of low power clock

8.3.10 WAKE Pin

Only when the device is in LPM0 mode, it can be activated by a positive voltage on the WAKE pin with a minimum pulse width t_WAKE. A valid wake condition is latched. Normal deactivation of the device can only occur through the SPI Interface by sending an SPI command to enter LMP0. Once in LMP0, the device stays in LPM0 when the WAKE pin is low, or restarts to TESTSTART when the WAKE pin is high.

The WAKE pin has an internal pulldown resistance R_PD-WAKE, and the voltage on the pin is not allowed to exceed 60 V. A higher voltage compliance level in the application can be achieved by applying an external series resistor between the WAKE pin and the external wake-up signal.

The device cannot be re-enabled by toggling the WAKE pin when the device is in LOCKED state (by SPI command).

Figure 18. Operating Mode Transitions

8.3.11 IRQ Pin

The IRQ pin has two different functions. In OPERATING mode, the pin is forced low when the voltage on the battery line is below the V_SSENSETHx threshold. The IRQ pin is low as long as PRESN is low. If PRESN goes high and the battery line is already below the V_SSENSETHx threshold, the IRQ pin is forced high for t_{VSSENSE_BLK}.

8.3.12 VBAT Undervoltage Warning

• Low battery condition on VSSENSE asserts IRQ output (interrupt for µC, open drain output)
• Sense input can be directly connected to VBAT through the resistor
• Detection threshold for undervoltage warning can be selected through the SPI.
• An integrated filter time avoids false reaction due to spikes on the VBAT line.

8.3.13 VIN Over or Undervoltage Protection

• Undervoltage is monitored on the V_IN line, for POR generation.
• Two V_IN overvoltage shutdown thresholds (V_OVTH) can be selected through the SPI. After POR, the lower threshold is enabled.
• During LPM0, only the POR condition is monitored.
• An integrated filter time avoids false reaction due to spikes on the V_IN line.
• In case of overvoltage, the external PMOS is switched off to protect the device. The BUCK1 controller is not switched off and it continues to run until the undervoltage on VREG or BUCK1 output is detected.

Figure 19. Overvoltage or Undervoltage Detection Circuitry

8.3.14 External Protection

The external PMOS switch is disabled if:

• The device detects V_IN overvoltage
• The device is in ERROR, LOCKED, POR, INIT, TESTSTART, TESTSTOP or LPM0 mode

Figure 20. PMOS Control Circuitry

8.3.15 Overtemperature Detection and Shutdown

There are two levels of thermal protection for the device.

Overtemperature is monitored locally on each regulator.

8.3.16 Independent Voltage Monitoring

The device contains independent voltage-monitoring circuits for BUCK1–3, LDO, VIO and BOOST. The reference voltage for the voltage monitoring unit is derived from an independent bandgap. BUCKs 1–3 use separate input pins for monitoring. The monitoring circuit is implemented as a window comparator with an upper and lower threshold.

If there is a violation of the upper (only LDO [RAMP, VTCHECK], or BUCK1–3) or lower threshold (only BUCK1–3, or VIO), the device enters ERROR mode, RESN and PRESN are asserted low, the external PMOS (main system switch) is switched off, and the EC is incremented.

In TESTSTART mode, a self-test of the independent voltage monitors is performed.

In case any of the supply rails for BUCK2, BUCK3, LDO or BOOST are not used in the application, the respective VMON2 and VMON3 or VSENSE4 and VSENSE5 pin of the unused supply must be connected to VMON1. Alternatively, the VSENSE4 pin can also be connected directly to ground in case the LDO is not used.

8.3.17 GND Loss Detection

All power grounds PGNDx are monitored. If the voltage difference to GND exceeds V_GLTH-low or V_GLTH-high, the device enters ERROR mode. RESN and PRESN are asserted low, the external PMOS (main system switch) is switched off, and the EC is incremented.

8.3.18 Reference Voltage

The device includes a precise voltage reference output to supply a system ADC. If this reference voltage is used in the application, a decoupling capacitor between 0.6 and 5 µF must be used. If this reference voltage is not used in the application, this decoupling capacitor can be left out. The VREF output is enabled in RAMP state. The output is protected against a short to GND.

8.3.19 Shutdown Comparator

An auxiliary, short circuit protected output supplied from DVDD is provided at the VT_REF pin. This output is used as a reference for an external resistive divider to the VT pin. In case a voltage > VTTH is detected on the VT pin, the main switch (external PMOS driven by GPFET) is switched off. This functionality can be used to monitor over and under temperature (using a NTC resistor) to avoid operation below or above device specifications.

If the voltage at VT_REF falls below V_{VT_REF SH} while the shutdown comparator is enabled, an ERROR transition occurs. The shutdown comparator is enabled in VTCHECK state, and can be turned off by SPI. Disabling the comparator saves power by also disabling the VT_REF output.

8.3.20 LED and High-Side Switch Control

This module controls an external PMOS in current-limited high-side switch.

The current levels can be adjusted with an external sense resistor. Enable and disable is done with the HS_EN bit. The switch is controlled by the HSPWM input pin. Driving HSPWM high turns on the external FET.

The device offers an open load diagnostic indicated by the HS_OL flag in the SPI register PWR_STAT. Open load is also indicated in case the voltage on VINPROT–VSSENSE does not drop below the threshold when PWM is low (self-test).

A counter monitors the overcurrent condition to detect the risk of overheating. While HSPWM = high and HS_EN = high the counter is incremented during overcurrent conditions, and decremented if the current is below the overcurrent threshold at a sampling interval of t_{S HS} (see Figure 22). When reaching a net current limit time of t_{HSS CL}, the driver is turned off and the HS_EN bit is cleared. This feature can be disabled by SPI bit HS_CLDIS. When HS_EN is cleared, the counter is reset.

Figure 21. High-Side Control Circuit

Figure 22. HS Overcurrent Counter

8.3.21 Window Watchdog

The WD is used to detect a malfunction of the MCU and DSP. Description:

• Timeout trigger mode with long timing starts on the rising edge at RESN
• Window trigger mode with fixed timing after the first and each subsequent rising edge at the WD pin
• Watchdog is triggered by rising edge at the WD pin

A watchdog reset happens by:

• A trigger pulse outside the WD trigger open window
• No trigger pulse during window time

After the RESN pin is released (rising edge) the DSP and MCU must trigger the WD by a rising edge on the WD pin within a fixed time t_timeout. With this first trigger, the window watchdog functionality is released.

Figure 23. WD Window Description

8.3.22 Timeout in Start-Up Modes

A timer is used to limit the time during which the device can stay in each of the start-up modes: TESTSTART, TESTSTOP, VTCHECK and RAMP. If the device enters one of these start-up modes and V_IN or VT is not in a proper range, the part enters LPM0 after t_timeout is elapsed and the WAKE pin is low.

8.4.1 Operating Modes

8.4.1.5 RAMP

In this mode the device runs through the power-up sequencing of the SMPS rails (see Figure 24).

8.4.1.5.1 Power-Up Sequencing

After the power-up sequence (see Figure 24), all blocks are fully functional. BUCK1 starts first. After t_SEQ2 elapses and BUCK1 is above the undervoltage threshold, BUCK2 and BOOST start. BUCK3 and VREF start one t_SEQ1 after BUCK2. After the release of RESN pin, the µC can enable the LDO per SPI by setting bit 4 LDO_EN in PWR_CONFIG register to 1 (per default, this LDO_EN is set to 0 after each reset to the µC).

In case any of the following conditions occurduring power-up sequencing, the device enters ERROR mode and the error counter (EC) is increased:

• Overtemperature on BUCK1, BUCK2, BUCK3 or VREG
• Overvoltage on BUCK1, BUCK2, BUCK3 or LDO
• Overcurrent on BUCK1
• SMPS clock fail
• VT_REF and VREG undervoltage
• Loss of GND

In case VT > VT_TH-H, the device transitions to TESTSTART.

Figure 24. Power-up Sequencing

After the power-up sequence is completed (except LDO) without detecting an error condition, the device enters ACTIVE mode.

8.4.1.5.2 Power-Down Sequencing

There is no dedicated power-down sequencing. All rails are switched off at the same time. The external FETs of BUCK1 are switched off and the outputs of BUCK2, BUCK3, BOOST (PHx) and the LDO are switched in a high-impedance state.

8.5.1 SPI

The SPI provides a communication channel between the TPS65311-Q1 and a controller. The TPS65311-Q1 is always the slave. The controller is always the master. The SPI master selects the TPS65311-Q1 by setting CSN (chip select) to low. SDI (slave in) is the data input, SDO (slave out) is the data output, and SCK (serial clock input) is the SPI clock provided by the master. If chip select is not active (high), the data output SDO is high impedance. Each communication consist of 16 bits.

1 bit parity (odd) (parity is built over all bits including: R/W, CMD_ID[5:0], DATA[7:0])

1 bit R/W; read = 0 and write = 1

6 bits CMD identifier

8 bits data

Figure 25. SPI Bit-Frame

Each command is valid if:

• A valid CMD_ID is sent
• The parity bit (odd) is correct
• Exactly 16 SPI clocks are counted between falling and rising edge of CSN

The response to each master command is given in the following SPI cycle. The response address is the CMD_ID of the previous sent message and the corresponding data byte. The response data is latched with the previous cycle such that a response to a write command is the status of the register before the write access. (Same response as a read access.) The response to an invalid command is the original command with the correct parity bit. The response to an invalid number of SPI clock cycles is a SPI_SCK_FAIL communication (CMD_ID = 0x03). Write access to a read-only register is not reported as an SPI error and is treated as a read access. The initial answer after the first SPI command sent is: CMD_ID[5:0] = 0x3F and Data[7:0] 0x5A.

8.6.1 Register Description