SLVSE46A November 2017 – January 2018 TPS65680
The panel discharge sequence is triggered either by pulling the LS_CNTRL pin low, VIN dropping below the VDET threshold, or one of the input signals dropping below its power-good threshold (LSPG = 0). The device enters DISCHARGE STEP1, the D1 timer is started, and all level shifter outputs, including VSS1, VSS2, and VGH active discharge are driven to the states defined by the registers. D1 time is set in register. After the D1 timer expires, the device enters DISCHARGE STEP2 state.