SLVSE46A November 2017 – January 2018 TPS65680
TPS65680 provides two groups of four GCP outputs intended for driving the high voltage clock inputs of the row driver circuitry. All GCP outputs are parametrically identical; Outputs 1-6 share a common charge sharing pin CS1, outputs 7-12 share a common charge sharing pin CS2. Each output supports high (VGH), low (VGL2), charge-sharing (output connected to CS1, CS2), and HiZ state. Gate-voltage shaping is accomplished by connecting the CSx pins individually through resistors to GND or any other suitable potential. Alternatively both CS pins can be shorted together and connected through a common resistor to GND or any other suitable potential.
By design, charge sharing is supported between channels of different groups only, i.e. GCK1-6 can charge share with any channel from group GCK7-12 but not with any other channel from the same group GCK1-6. Charge sharing is accomplished by connecting CS1 to CS2 through a single resistor. Figure 10 shows a common charge sharing scheme for 12 clocks. Channel assignment is determined by the pattern sequence programed into the part.
At power-up all GCK outputs are in HiZ state and remain in this state until VGH, VGL1 and VGL2 are powered up. Then the outputs are released to the programmed output state as defined in and registers and remain in this state until the sequencer takes control after the programmable EN_DLY timer in register expired. During panel-discharge, the GCK outputs can be configured to be in Low, or High state separately for DISCHARGE STEP1 and DISCHARGE STEP2 using the GCK1_D1 and GCK_D2 bits of the and registers.