SLVSE46A November 2017 – January 2018 TPS65680
An increment instruction is used to add an arbitrary 8-bit value to register <REG_ADDR>. Overflow is supported. <REG ADDR> denotes the logical address listed in Table 1 and is specified as a four-bit value. The use of non-specified addresses is legal but not recommended. Processing an INC instruction requires one clock cycle. Within the sequence, the level shifter output state preceding the INC instruction is extended by one clock cycle while processing the INC instruction as shown in the example below.
ADDR INST CLK OUTPUT STATE 1 CXE<1> 1 <1> 2 LDR(5,FF) 2 <1> <-- Load Reg 0x05 with data 0xFF 3 CXE<2> 3 <2> 4 INC(5,1) 4 <2> <-- increment Reg 0x05 by 1 5 CXE<3> 5 <3> Reg 0x05 now contains value 0x00.