SLVSE46A November 2017 – January 2018 TPS65680
This instruction is used to write data to a register during run-time. It is most commonly used to
<REG ADDR> denotes the logical address listed in Table 1 and is specified as a four-bit value. The use of non-specified addresses is legal but not recommended. Processing of the LDR instruction requires one clock cycle. Within the sequence, the level shifter output state preceding the LDR instruction is extended by one clock cycle while processing the LDR instruction as shown in the example below.
ADDR INST CLK OUTPUT STATE 1 CXE<1> 1 <1> 2 CXE<2> 2 <2> 3 LDR(5,FF) 3 <2> <-- Load Reg 0x05 with data 0xFF 4 CXE<3> 4 <3>