In the event of high loading during loss of input voltage, there is a risk to go below the voltage level necessary for the internal logic of the device to work properly before the device is disabled. This means that when the VCC1 voltage supply level becomes lower than the VSYS_LO threshold, the input voltage may continue dropping to very low voltages during the 180 us ±10% delay before the device is disabled.
If a large input voltage drop occurs before the device is disabled, the internal logic can no longer properly drive the FETs of the SMPS, and it is possible that the high-side FET and low-side FET of the SMPS are on at the same time. In the event that the high-side and low-side FETs for an SMPS are on at the same time, there is a direct path from SMPSx_IN to SMPSx_GND, allowing cross-conduction and possible damage of the device.
In order to prevent damage or irregular switching behavior, it is important that the voltage at the SMPSx_IN pin stays above 1.8 V, including negative transients, before the device is disabled. The minimum voltage seen at the SMPSx_IN pin is dependent on VCC1 and the PCB inductance between the SMPSx_IN pin and the input capacitor. Use Equation 2 to determine the minimum capacitance needed on VCC1 to ensure that the device continues switching properly before it is disabled.
When measuring the SMPSx_IN and VCC1 during power down, use active differential probes and a high resolution oscilloscope (4GS/sec or more). VCC1 can be measured over the 10uF input capacitor. However, SMPSx_IN must be measured at the pin in order to measure the transients on this rail accurately. To measure SMPSx_IN, place the negative lead of the differential probe at a nearby GND, such as the GND of the SMPSx_IN input capacitor. Place the positive lead of the differential probe as close as possible to the SMPSx_IN pin. With this set up, verify that SMPSx_IN, including the ripple on this signal, does not drop below 1.8V before the SMPS stops switching. See Figure 7-5 for an example of how to take this measurement. For ways to decrease the amplitude of the transient spikes, see Table 9-1 for recommended parasitic inductance requirements.