In POWERHOLD mode, the acknowledge of the power on is achieved through a dedicated pin, POWERHOLD. Upon receipt of an ON request, the device initiates the power-up sequence and asserts the RESET_OUT pin high once it is in the ACTIVE state (reset released). While in the ACTIVE state, the device remains active for 8 seconds and then automatically shuts down. During this time-frame, to keep the device active, the host processor must assert and keep the POWERHOLD pin high. If the POWERHOLD pin is then set back to low, it is interpreted as an OFF request by the device.
Figure 6-21 shows the POWERHOLD mode timing diagrams.