The watchdog timer has two modes of operation, periodic mode and interrupt mode.
In periodic mode, an interrupt is generated with a regular period N that is defined by the WATCHDOG.TIMER setting. This interrupt is generated at the beginning of the period (when the watchdog internal counter equals 1). The IC initiates a shutdown at the end of the period (when the internal counter has reached N) only if the interrupt has not been cleared within the defined time frame (0 to N). In this mode, when the interrupt is cleared, the internal counter is not reset. The counter continues to count until it reaches the maximum value (defined by the TIMER setting) and automatically rolls over to 0 in order to start a new counting period. Regardless of when the interrupt is cleared within a given period (N), the next interrupt is generated only when the ongoing period completes (reaches N). The internal watchdog counter is initialized and kept at 0 as long as the RESET_OUT terminal is low. The counter begins counting as soon as the RESET_OUT terminal is released.
In interrupt mode, any interrupt source resets the watchdog counter and begins the counting. If the sources of the interrupts are not cleared (INT line released) before the end of the predefined period N (set by WATCHDOG.TIMER setting) then the IC initiates a shutdown. If the sources of the interrupts are cleared within the predefined period, then the watchdog counter is discarded (DC) and no shutdown sequence is initiated.
By default, the watchdog is disabled.
Figure 6-26 shows the watchdog timings.