SLVSCO4D July 2015 – February 2019 TPS65917-Q1
In PWM mode, the SMPSs are synchronized on an external input clock, SYNCDCDC (muxed with GPIO_3), whereas in ECO mode, the switching frequency is based on an internal RC oscillator.
For PWM mode, a PLL is present to buffer the external clock input from SYNCDCDC pin, and to create 5 clock signals for the 5 SMPSs with different phases.
Figure 5-10 shows the frequency of SYNCDCDC input clock (fSYNC) and the frequency of PLL output signal (fSW).
When no clock is present on the SYNCDCDC pin, the PLL generates a clock with a frequency equal to the fallback frequency (fFALLBACK).
When a clock is present on the SYNCDCDC pin with a frequency between the low and high PLL saturation frequencies (fSAT,LO and fSAT,HI), then the PLL is synchronized on the SYNCDCDC clock and generates a clock with frequency equal to fSYNC.
If fSYNC is higher than fSAT,HI, then the PLL generates a clock with a frequency equal to fSAT,HI.
If fSYNC is smaller than fSAT,LO, then the PLL generates a clock with a frequency equal to fSAT,LO.
Dithering can be achieved by changing the frequency of the clock provided on the SYNCDCDC pin. The sync clock dither specification parameters are based on a triangular dither pattern, but other patterns that comply with the minimum and maximum sync frequency range and the maximum dither slope can also be used, as seen in Figure 5-11.