SLVSCO4D July 2015 – February 2019 TPS65917-Q1
SMPS1, SMPS2, SMPS1&2, and SMPS3 include several other features.
The SMPS sink current limitation is controlled with the SMPS_NEGATIVE_CURRENT_LIMIT_EN register. The limitation is enabled by default.
Channel 4 of the GPADC can be used to monitor the output current of SMPS1, SMPS2, SMPS1&2, SMPS3, or SMPS5. Load current monitoring is enabled for a given SMPS in the SMPS_ILMONITOR_EN register. SMPS output-power monitoring is intended to be used during the steady state of the output voltage, and is supported in PWM mode only.
Use Equation 1 to calculate the SMPS output-current result.
Use Equation 2 to calculate the temperature compensated result.
For the values of IFS0 and IOS0, see Section 4.10.
The SMPS thermal monitoring is enabled (default) and disabled with the SMPS_THERMAL_EN register. When enabled, the SMPS thermal status is available in the SMPS_THERMAL_STATUS register. SMPS12, SMPS3, and SMPS5 have thermal protection. A unique thermal sensor is shared and protecting both SMPS1 and SMPS2. SMPS4 has no dedicated thermal protection.
Each SMPS has a detection for load current above ILIM, indicating overcurrent or a shorted SMPS output. The SMPS_SHORT_STATUS register indicates any SMPS short condition. Depending on the setting of the INT2_MASK.SHORT register, an interrupt is generated upon any shorted SMPS. If a short occurs on any enabled SMPSs, the corresponding short status bit is set in the SMPS_SHORT_STATUS register. A switch-off signal is then sent to the corresponding SMPS, and it remains off until the corresponding bit in the SMPS_SHORT_STATUS register is cleared. This register is cleared on read, or by issuing a POR. The same behavior applies to LDO shorts using the LDO_SHORT_STATUS registers.
A short must occur on any enabled SMPS or LDO for at least 155 us to 185 us for the short detection to shut off the rail. During startup of the device, there is a 2 ms counter that masks any short-circuit shutdown. This counter starts when the device is enabled and the counter is reset when any SMPSx or LDOx rail becomes ACTIVE. When no rail has been enabled for 2 ms, the counter reaches its threshold and the short-circuit shutdown is no longer masked for the enabled SMPSs and LDOs.