SLVSCO4D July 2015 – February 2019 TPS65917-Q1
In POWERHOLD mode, the power-on acknowledge is received through a dedicated pin, POWERHOLD. When an ON request is received, the device initiates the power-up sequence and asserts the RESET_OUT pin high while the device is in the ACTIVE state (reset released). The device remains in ACTIVE state for a fixed delay of 8 seconds and then automatically shuts down. During this timeframe, to keep the device active, the host processor must assert and keep the POWERHOLD pin high. The device interprets a the high to low transition of the POWERHOLD pin as an OFF request.
Figure 5-5 shows the POWERHOLD mode timing diagram.