5.4.1 Step-Down Regulators
The synchronous step-down converter used in the power-management core has high efficiency while enabling operation with cost-competitive and small external components. The SMPSx_IN supply pins of all the converters should be individually connected to the VSYS supply (VCCA pin). Two of these configurable step-down converters can be multiphased to create up to a 7-A rail. All of the step-down converters can synchronize to an external clock source between 1.7 MHz and 2.7 MHz, or an internal fallback clock at 2.2 MHz.
The step-down converter supports two operating modes, which can be selected independently. These two operating modes are defined as follows:
Forced PWM mode: In forced PWM mode, the device avoids pulse skipping and allows easy filtering of the switch noise by external filter components. The drawback is the higher IDDQ at low-output current levels.
Eco-mode (lowest quiescent-current mode): Each step-down converter can be individually controlled to enter a low quiescent-current mode. In ECO-mode, the quiescent current is reduced and the output voltage is supervised by a comparator while most of the control circuitry disabled to save power. The regulators should not be enabled under ECO-mode to ensure the stability of the output. ECO-mode should only be enabled when a converter has less than 5 mA of load current and VO can remain constant. In addition, ECO-mode should be disabled before a load-transient step to allow the converter to respond in a timely manner to the excess current draw.
To ensure proper operation of the converter while it is in ECO-mode, the output voltage level must be less then 70% of the input supply voltage level. If the VO of the converter is greater than 2.8 V, a safety feature of the device monitors the supply voltage of the converter and automatically switch off the converter if the input voltage falls below 4 V. The purpose of this safety mechanism is to prevent damage to the converter because of design limitation while the converter is in ECO mode.
In addition to the operating modes, the following parameters can be selected for the regulators:
- Powergood: See Section 126.96.36.199.
- Output discharge: Each switching regulator is equipped with an output discharge enable bit. When this bit is set to 1, the output of the regulator is discharged to ground with the equivalent of a 9-Ω resistor when the regulator is disabled. If the regulator enable bit is set, the discharge bit of the regulator is ignored.
- Output-current monitoring: The GPADC can monitor the SMPS output current. One SMPS at a time can be selected for measurement from the following: SMPS1, SMPS2, SMPS1&2, SMPS3, and SMPS5. Selection is controlled through the GPADC_SMPS_ILMONITOR_EN register.
- Enable control of the Step-down converters: The step-down converter enable and disable is part of the flexible power-up and power-down state-machine. Each converter can be programmed such that it is powered up automatically to a preselected voltage in one of the time slots after a power-on condition occurs. Alternatively, each SMPS can be controlled by a dedicated pin. The NSLEEP, ENABLE1, and ENABLE2 pins can be mapped to any resource (LDOs, SMPS converter, 32-kHz clock output, or GPIO) to enable or disable the pin. Each SMPS can also be enabled and disabled through access to the I2C registers.