SLVSEA7A December   2019  – April 2021 TPS6594-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Diagram
  5. Revision History
  6. Description (continued)
  7. Pin Configuration and Functions
    1. 7.1 Digital Signal Descriptions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 8.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 8.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 8.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 8.9  Reference Generator (BandGap)
    10. 8.10 Monitoring Functions
    11. 8.11 Clocks, Oscillators, and PLL
    12. 8.12 Thermal Monitoring and Shutdown
    13. 8.13 System Control Thresholds
    14. 8.14 Current Consumption
    15. 8.15 Backup Battery Charger
    16. 8.16 Digital Input Signal Parameters
    17. 8.17 Digital Output Signal Parameters
    18. 8.18 I/O Pullup and Pulldown Resistance
    19. 8.19 I2C Interface
    20. 8.20 Serial Peripheral Interface (SPI)
  9. Typical Characteristics
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  System Supply Voltage Monitor and Over-Voltage Protection
      2. 10.3.2  Power Resources (Bucks and LDOs)
        1. 10.3.2.1 Buck Regulators
          1. 10.3.2.1.1 Overview
          2. 10.3.2.1.2 Multi-Phase Operation and Phase-Adding or Shedding
          3. 10.3.2.1.3 Transition Between PWM and PFM Modes
          4. 10.3.2.1.4 Multi-Phase Buck Regulator Configurations
          5. 10.3.2.1.5 Spread-Spectrum Mode
          6. 10.3.2.1.6 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 10.3.2.1.7 Buck Output Voltage Setting
        2. 10.3.2.2 Sync Clock Functionality
        3.      
        4. 10.3.2.3 Low Dropout Regulators (LDOs)
          1. 10.3.2.3.1 LDOVINT
          2. 10.3.2.3.2 LDOVRTC
          3. 10.3.2.3.3 LDO1, LDO2, and LDO3
          4. 10.3.2.3.4 Low-Noise LDO (LDO4)
      3. 10.3.3  Residual Voltage Checking
      4. 10.3.4  Output Voltage Monitor and PGOOD Generation
      5. 10.3.5  Thermal Monitoring
        1. 10.3.5.1 Thermal Warning Function
        2. 10.3.5.2 Thermal Shutdown
      6. 10.3.6  Backup Supply Power-Path
      7. 10.3.7  General-Purpose I/Os (GPIO Pins)
      8. 10.3.8  nINT, EN_DRV, and nRSTOUT Pins
      9. 10.3.9  Interrupts
      10. 10.3.10 RTC
        1. 10.3.10.1 General Description
        2. 10.3.10.2 Time Calendar Registers
          1. 10.3.10.2.1 TC Registers Read Access
          2. 10.3.10.2.2 TC Registers Write Access
        3. 10.3.10.3 RTC Alarm
        4. 10.3.10.4 RTC Interrupts
        5. 10.3.10.5 RTC 32-kHz Oscillator Drift Compensation
      11. 10.3.11 Watchdog (WD)
        1. 10.3.11.1 Watchdog Fail Counter and Status
        2. 10.3.11.2 Watchdog Start-Up and Configuration
        3. 10.3.11.3 MCU to Watchdog Synchronization
        4. 10.3.11.4 Watchdog Disable Function
        5. 10.3.11.5 Watchdog Sequence
        6. 10.3.11.6 Watchdog Trigger Mode
        7. 10.3.11.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8. 10.3.11.8 Watchdog Question-Answer Mode
          1. 10.3.11.8.1 Watchdog Q&A Related Definitions
          2. 10.3.11.8.2 Question Generation
          3. 10.3.11.8.3 Answer Comparison
            1. 10.3.11.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 10.3.11.8.3.2 Watchdog Sequence Events and Status Updates
            3. 10.3.11.8.3.3 Watchdog Q&A Sequence Scenarios
      12. 10.3.12 Error Signal Monitor (ESM)
        1. 10.3.12.1 ESM Error-Handling Procedure
          1. 10.3.12.1.1 Level Mode
          2. 10.3.12.1.2 PWM Mode
            1. 10.3.12.1.2.1 Good-Events and Bad-Events
            2. 10.3.12.1.2.2 ESM Error-Counter
            3. 10.3.12.1.2.3 ESM Start-Up in PWM Mode
            4. 10.3.12.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
    4. 10.4 Device Functional Modes
      1. 10.4.1 Device State Machine
        1. 10.4.1.1 Fixed Device Power FSM
          1. 10.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 10.4.1.2 Pre-Configurable Mission States
          1. 10.4.1.2.1 PFSM Commands
            1. 10.4.1.2.1.1  REG_WRITE_IMM Command
            2. 10.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 10.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 10.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 10.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 10.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 10.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 10.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 10.4.1.2.1.9  SREG_READ_REG Command
            10. 10.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 10.4.1.2.1.11 WAIT Command
            12. 10.4.1.2.1.12 DELAY_IMM Command
            13. 10.4.1.2.1.13 DELAY_SREG Command
            14. 10.4.1.2.1.14 TRIG_SET Command
            15. 10.4.1.2.1.15 TRIG_MASK Command
            16. 10.4.1.2.1.16 END Command
          2. 10.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 10.4.1.2.3 Mission State Configuration
          4. 10.4.1.2.4 Pre-Configured Hardware Transitions
            1. 10.4.1.2.4.1 ON Requests
            2. 10.4.1.2.4.2 OFF Requests
            3. 10.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 10.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 10.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 10.4.1.3 Error Handling Operations
          1. 10.4.1.3.1 Power Rail Output Error
          2. 10.4.1.3.2 Boot BIST Error
          3. 10.4.1.3.3 Runtime BIST Error
          4. 10.4.1.3.4 Catastrophic Error
          5. 10.4.1.3.5 Watchdog (WDOG) Error
          6. 10.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 10.4.1.3.7 Warnings
        4. 10.4.1.4 Device Startup Timing
        5. 10.4.1.5 Power Sequences
        6. 10.4.1.6 First Supply Detection
        7. 10.4.1.7 Register Power Domains and Reset Levels
      2. 10.4.2 Multi-PMIC Synchronization
        1. 10.4.2.1 SPMI Interface System Setup
        2. 10.4.2.2 Transmission Protocol and CRC
        3. 10.4.2.3 SPMI Slave Communication to SPMI Master
          1. 10.4.2.3.1 Incomplete Communication from SPMI Slave to SPMI Master
        4. 10.4.2.4 SPMI BIST Overview
    5. 10.5 Control Interfaces
      1. 10.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 10.5.2 I2C-Compatible Interface
        1. 10.5.2.1 Data Validity
        2. 10.5.2.2 Start and Stop Conditions
        3. 10.5.2.3 Transferring Data
        4. 10.5.2.4 Auto-Increment Feature
      3. 10.5.3 Serial Peripheral Interface (SPI)
    6. 10.6 Configurable Registers
      1. 10.6.1 Register Page Partitioning
      2. 10.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 10.6.3 CRC Protection for User Registers
      4. 10.6.4 Register Write Protection
        1. 10.6.4.1 ESM and WDOG Configuration Registers
        2. 10.6.4.2 User Registers
    7. 10.7 Register Maps
      1. 10.7.1 TPS6594-Q1 Registers
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Powering a Processor
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 VCCA, VSYS_SENSE, and OVPGDRV
          2. 11.2.1.2.2 Internal LDOs
          3. 11.2.1.2.3 Crystal Oscillator
          4. 11.2.1.2.4 Buck Input Capacitors
          5. 11.2.1.2.5 Buck Output Capacitors
          6. 11.2.1.2.6 Buck Inductors
          7. 11.2.1.2.7 LDO Input Capacitors
          8. 11.2.1.2.8 LDO Output Capacitors
          9. 11.2.1.2.9 Digital Signal Connections
      2. 11.2.2 Application Curves
    3. 11.3 Power Supply Recommendations
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
    3. 12.3 Documentation Support
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified with the Following Results:
    • Device Operates from 3 V to 5.5 V Input Supply
    • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
    • Device HBM Classification Level 2
    • Device CDM Classification Level C4A
  • SafeTI Semiconductor Component
    • Designed for Functional Safety Applications
    • Documentation Available to Aid ISO 26262 System Design up to ASIL D
    • Systematic Capability and Hardware Integrity up to ASIL D
    • Input Supply Monitor and Over-Voltage Protection
    • Windowed Voltage and Over-Current Monitors
    • Integrated Q&A or Trigger Mode Watchdog Module
    • Dual Channel Level or PWM Error Signal Monitoring (ESM) Supporting Processors with Integrated Safety-MCU
    • Thermal Monitoring With High Temperature Warning and Thermal Shutdown
    • NVM Bit-Integrity Error Detection With Options to Proceed or Hold Power-Up Sequence and Reset Release
  • Low-Power Consumption
    • 2 μA Typical Shutdown Current
    • 7 μA Typical in Back Up Supply Only Mode
    • 20 μA Typical in Low Power Standby Mode
  • Five Step-Down Switched-Mode Power Supply (BUCK) Regulators:
    • 0.3 V to 3.34 V Output Range in 5, 10, or 20 mV Steps
    • One with 4 A, Three with 3.5 A, and One with 2 A Capability
    • Four of the Bucks with Flexible Multi-Phase Capability which can Source up to 14 A from a Single Rail
    • Short-Circuit Protection and Over-Current Protection
    • Internal Soft-Start for In-Rush Current Limitation
    • 2.2 MHz / 4.4 MHz Switching Frequency
    • Ability to Synchronize to External Clock Input
  • Three Low-Dropout (LDO) Linear Regulators With Configurable Bypass Mode
    • 0.6 V to 3.3 V Output Range with 50 mV Steps in Linear Regulation Mode
    • 1.7 V to 3.3 V Output Range in Bypass Mode
    • 500 mA Capability With Short-Circuit and Over-Current Protection
  • One Low-Dropout (LDO) Linear Regulator with Low-Noise Performance
    • 1.2 V to 3.3 V Output Range in 25 mV Steps
    • 300 mA Capability With Short-Circuit and Over-Current Protection
  • Power Sequence Control:
    • Configurable Power-Up and Power-Down Sequences between Power States (NVM)
    • Digital Output Signals can be Included in the Power Sequences
    • Digital Input Signals can be used to trigger Power Seqence Transitions
  • 32 kHz Crystal Oscillator with Option to Output a Buffered 32-kHz Clock Output
  • Real-Time Clock (RTC) with Alarm and Periodic Wake-Up Mechanism
  • One SPI or Two I2C Control Interfaces, with Second I2C Interface Dedicated for Q&A Watchdog Communication
  • Package Option:
    • 8-mm × 8-mm 56-pin VQFNP With 0.5-mm Pitch