SLVSD02D March 2015 – June 2019 TPS65982
The TPS65982 has a Power-on-Reset (POR) circuit that monitors LDO_3V3 and issues an internal reset signal. The digital core, memory banks, and peripherals receive clock and RESET interrupt is issued to the digital core and the boot code starts executing. Figure 63 provides the TPS65982 boot code sequence.
The TPS65982 boot code is loaded from OTP on POR, and begins initializing TPS65982 settings. This initialization includes enabling and resetting internal registers, loading trim values, waiting for the trim values to settle, and configuring the device I2C addresses.
The unique I2C address is based on the customer programmable OTP, DEBUG_CTLX pins, and resistor configuration on the I2C_ADDR pin.
Once initial device configuration is complete the boot code determines if the TPS65982 is booting under dead battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65982 is booting under dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS power to the system.