SLVSD02D March 2015 – June 2019 TPS65982
The TPS65982 UART paths (UART_RX/TX and LSX_P2R/R2P) and GPIO0/1 all have digital inputs that pass through a cross-bar multiplexer inside the digital core. Each of these pins is configurable as an input or output of the cross-bar multiplexer. The digital cross-bar multiplexer then connects to the port data multiplexers as shown in Figure 44. The connections are configurable via firmware. The default state at power-up is to connect a buffered version of UART_RX to UART_TX providing a bypass through the TPS65982 for daisy chaining during power on reset.