SLVSD02D March 2015 – June 2019 TPS65982
To enable the setting of multiple I2C addresses using a single TPS65982 pin, a resistance is placed externally on the I2C_ADDR pin. The internal ADC then decodes the address from this resistance value. Figure 76 shows the decoding. DEBUG_CTL1/2 are checked at the same time for the DC condition on this pin (high or low) for setting other bits of the address described previously. Note, DEBUG_CTL1/2 are GPIO and the address decoding is done by firmware in the digital core.
Table 10 lists the external resistance needed to set bits [3:1] of the I2C Unique Address. For the Primary TPS65982 (UART Master), the I2C_ADDR pin is grounded and this TPS65982 is connected to the SPI Flash. In a two Type-C port system sharing one SPI Flash, I2C_ADDR is left as an open-circuit (UART Slave 1) and this TPS65982 is referred to as the Secondary.
|SPI Owner, UART Master 0 (Primary)||0 Ω||0x00|
|UART Slave 7||38.3 kΩ||0x01|
|UART Slave 6||84.5 kΩ||0x02|
|UART Slave 5||140 kΩ||0x03|
|UART Slave 4||205 kΩ||0x04|
|UART Slave 3||280 kΩ||0x05|
|UART Slave 2||374 kΩ||0x06|
|UART Slave 1 (Secondary)||Open||0x07|