SLVSD02D March   2015  – June 2019 TPS65982

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Diagram
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Legend for Pinout Drawing
    2.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Requirements and Characteristics
    6. 7.6  Power Supervisor Characteristics
    7. 7.7  Power Consumption Characteristics
    8. 7.8  Cable Detection Characteristics
    9. 7.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 7.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 7.11 Port Power Switch Characteristics
    12. 7.12 Port Data Multiplexer Switching Characteristics
    13. 7.13 Port Data Multiplexer Clamp Characteristics
    14. 7.14 Port Data Multiplexer SBU Detection Characteristics
    15. 7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
    16. 7.16 Port Data Multiplexer USB Endpoint Characteristics
    17. 7.17 Port Data Multiplexer BC1.2 Detection Characteristics
    18. 7.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 7.19 Input/Output (I/O) Characteristics
    20. 7.20 I2C Slave Characteristics
    21. 7.21 SPI Master Characteristics
    22. 7.22 BUSPOWERZ Configuration Characteristics
    23. 7.23 Thermal Shutdown Characteristics
    24. 7.24 Oscillator Characteristics
    25. 7.25 Single-Wire Debugger (SWD) Timing Requirements
    26. 7.26 HPD Timing Requirements
    27. 7.27 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  USB-PD Physical Layer
        1. 9.3.1.1 USB-PD Encoding and Signaling
        2. 9.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.1.4 USB-PD BMC Transmitter
        5. 9.3.1.5 USB-PD BMC Receiver
      2. 9.3.2  Cable Plug and Orientation Detection
        1. 9.3.2.1 Configured as a DFP
        2. 9.3.2.2 Configured as a UFP
        3. 9.3.2.3 Dead-Battery or No-Battery Support
      3. 9.3.3  Port Power Switches
        1. 9.3.3.1  5V Power Delivery
        2. 9.3.3.2  5V Power Switch as a Source
        3. 9.3.3.3  PP_5V0 Current Sense
        4. 9.3.3.4  PP_5V0 Current Limit
        5. 9.3.3.5  Internal HV Power Delivery
        6. 9.3.3.6  Internal HV Power Switch as a Source
        7. 9.3.3.7  Internal HV Power Switch as a Sink
        8. 9.3.3.8  Internal HV Power Switch Current Sense
        9. 9.3.3.9  Internal HV Power Switch Current Limit
        10. 9.3.3.10 External HV Power Delivery
        11. 9.3.3.11 External HV Power Switch as a Source with RSENSE
        12. 9.3.3.12 External HV Power Switch as a Sink with RSENSE
        13. 9.3.3.13 External HV Power Switch as a Sink without RSENSE
        14. 9.3.3.14 External Current Sense
        15. 9.3.3.15 External Current Limit
        16. 9.3.3.16 Soft Start
        17. 9.3.3.17 BUSPOWERZ
        18. 9.3.3.18 Voltage Transitions on VBUS through Port Power Switches
        19. 9.3.3.19 HV Transition to PP_RV0 Pull-Down on VBUS
        20. 9.3.3.20 VBUS Transition to VSAFE0V
        21. 9.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery
        22. 9.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        23. 9.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 9.3.4  USB Type-C Port Data Multiplexer
        1. 9.3.4.1  USB Top and Bottom Ports
        2. 9.3.4.2  Multiplexer Connection Orientation
        3. 9.3.4.3  Digital Crossbar Multiplexer
        4. 9.3.4.4  SBU Crossbar Multiplexer
        5. 9.3.4.5  Signal Monitoring and Pullup/Pulldown
        6. 9.3.4.6  Port Multiplexer Clamp
        7. 9.3.4.7  USB2.0 Low-Speed Endpoint
        8. 9.3.4.8  Battery Charger (BC1.2) Detection Block
        9. 9.3.4.9  BC1.2 Data Contact Detect
        10. 9.3.4.10 BC1.2 Primary and Secondary Detection
      5. 9.3.5  Power Management
        1. 9.3.5.1 Power-On and Supervisory Functions
        2. 9.3.5.2 Supply Switch-Over
        3. 9.3.5.3 RESETZ and MRESET
      6. 9.3.6  Digital Core
      7. 9.3.7  USB-PD BMC Modem Interface
      8. 9.3.8  System Glue Logic
      9. 9.3.9  Power Reset Congrol Module (PRCM)
      10. 9.3.10 Interrupt Monitor
      11. 9.3.11 ADC Sense
      12. 9.3.12 UART
      13. 9.3.13 I2C Slave
      14. 9.3.14 SPI Master
      15. 9.3.15 Single-Wire Debugger Interface
      16. 9.3.16 DisplayPort HPD Timers
      17. 9.3.17 ADC
        1. 9.3.17.1 ADC Divider Ratios
        2. 9.3.17.2 ADC Operating Modes
        3. 9.3.17.3 Single Channel Readout
        4. 9.3.17.4 Round Robin Automatic Readout
        5. 9.3.17.5 One Time Automatic Readout
      18. 9.3.18 I/O Buffers
        1. 9.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 9.3.18.2 IOBUF_OD
        3. 9.3.18.3 IOBUF_UTX
        4. 9.3.18.4 IOBUF_URX
        5. 9.3.18.5 IOBUF_PORT
        6. 9.3.18.6 IOBUF_I2C
        7. 9.3.18.7 IOBUF_GPIOHSPI
        8. 9.3.18.8 IOBUF_GPIOHSSWD
      19. 9.3.19 Thermal Shutdown
      20. 9.3.20 Oscillators
    4. 9.4 Device Functional Modes
      1. 9.4.1 Boot Code
      2. 9.4.2 Initialization
      3. 9.4.3 I2C Configuration
      4. 9.4.4 Dead-Battery Condition
      5. 9.4.5 Application Code
      6. 9.4.6 Flash Memory Read
      7. 9.4.7 Invalid Flash Memory
      8. 9.4.8 UART Download
    5. 9.5 Programming
      1. 9.5.1 SPI Master Interface
      2. 9.5.2 I2C Slave Interface
        1. 9.5.2.1 I2C Interface Description
        2. 9.5.2.2 I2C Clock Stretching
        3. 9.5.2.3 I2C Address Setting
        4. 9.5.2.4 Unique Address Interface
        5. 9.5.2.5 I2C Pin Address Setting
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Fully-Featured USB Type-C and PD Charger Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 External FET Path Components (PP_EXT and RSENSE)
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 TPS65982 External Flash
          2. 10.2.1.2.2 I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD) Resistors
          3. 10.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 10.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 10.2.1.2.5 Soft Start (SS) Capacitor
          6. 10.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
          7. 10.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
          8. 10.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          9. 10.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 Source Power Delivery Profiles for Type-C Ports
          2. 10.2.2.1.2 Sink Power Delivery Profile for Type-C Ports
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 TPS65982 and System Controller Interaction
          2. 10.2.2.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 10.2.2.2.3 9.3.2.3 DC Barrel Jack and Type-C PD Charging
          4. 10.2.2.2.4 Primary TPS65982 Flash Master and Secondary Port
          5. 10.2.2.2.5 TPS65982 Dead Battery Support Primary and Secondary Port
          6. 10.2.2.2.6 Debugging Methods
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 3.3-V Power
      1. 11.1.1 VIN_3V3 Input Switch
      2. 11.1.2 VOUT_3V3 Output Switch
      3. 11.1.3 VBUS 3.3-V LDO
    2. 11.2 1.8 V Core Power
      1. 11.2.1 1.8 V Digital LDO
      2. 11.2.2 1.8 V Analog LDO
    3. 11.3 VDDIO
      1. 11.3.1 Recommended Supply Load Capacitance
      2. 11.3.2 Schottky for Current Surge Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  TPS65982 Recommended Footprints
        1. 12.1.1.1 Standard TPS65982 Footprint (Circular Pads)
      2. 12.1.2  Alternate TPS65982 Footprint (Oval Pads)
      3. 12.1.3  Top TPS65982 Placement and Bottom Component Placement and Layout
      4. 12.1.4  Oval Pad Footprint Layout and Placement
      5. 12.1.5  Component Placement
      6. 12.1.6  Designs Rules and Guidance
      7. 12.1.7  Routing PP_HV, PP_EXT, PP_5V0, and VBUS
      8. 12.1.8  Routing Top and Bottom Passive Components
      9. 12.1.9  Void Via Placement
      10. 12.1.10 Top Layer Routing
      11. 12.1.11 Inner Signal Layer Routing
      12. 12.1.12 Bottom Layer Routing
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

ZQZ and ZBH Package
96-Pin BGA MicroStar Junior and NFBGA
Top View

Legend for Pinout Drawing

TPS65982 pinout_legend_slvsd93.gif

Pin Functions

PIN TYPE CATEGORY POR STATE DESCRIPTION
NO. NAME
A1 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
A10 SENSEN Analog input External HV-FET control and sense pins and soft start Analog input Positive sense for external high-voltage power-path current-sense resistance. Short pin to VBUS when unused.
A11 PP_5V0 Power High-current power pins 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
A2 LDO_1V8D Power Low-current power pins Output of the 1.8-V LDO for core digital circuits. Bypass with capacitance CLDO_1V8D to GND.
A3 SPI_CLK Digital output Digital core I/O and control pins Digital input SPI serial clock. Ground pin when unused
A4 SPI_MISO Digital input Digital core I/O and control pins Digital input SPI serial master input from slave. This pin is used during boot sequence to determine if the flash memory is valid. Refer to the Boot Code section for more details. Ground pin when unused.
A5 I2C_SDA2 Digital I/O Digital core I/O and control pins Digital input I2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
A6 PP_HV Power High-current power pins HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused.
A7
A8
A9 HV_GATE2 Analog output External HV-FET control and sense pins and soft start Short to VBUS External NFET gate control for high-voltage power path. Float pin when unused.
B1 VDDIO Power  Low-current power pins VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply input, bypass with capacitance CVDDIO to GND.
B10 SENSEP Analog input External HV-FET control and sense pins and soft start Analog input Positive sense for external high-voltage power-path current-sense resistance. Short pin to VBUS when unused.
B11 PP_5V0 Power High-current power pins 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
B2 GPIO0 Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 0. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
B3 SPI_SSZ Digital output Digital core I/O and control pins Digital input SPI slave select. Ground pin when unused.
B4 SPI_MOSI Digital output Digital core I/O and control pins Digital input SPI serial master output to slave. Ground pin when unused.
B5 I2C_SCL2 Digital I/O Digital core I/O and control pins Digital input I2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
B6 I2C_IRQ2Z Digital output Digital core I/O and control pins Hi-Z I2C port 2 interrupt. Active-low. Implement externally as an open-drain with a pullup resistance. Float pin when unused.
B7 PP_HV Power High-current power pins HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused.
B8 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
B9 HV_GATE1 Analog output External HV-FET control and sense pins and soft start Short to SENSEP External NFET gate control for high-voltage power path. Float pin when unused.
C1 I2C_IRQ1Z Digital output Digital core I/O and control pins Hi-Z I2C port 1 interrupt. Active-low. Implement externally as an open-drain with a pullup resistance. Float pin when unused.
C10 GPIO4
(HPD TXRX)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 4. Configured as hot-plug detect (HPD) TX, HPD RX, or both when DisplayPort mode is supported. Ground pin with a 1-MΩ resistor when unused in the application.
C11 PP_5V0 Power High-current power pins 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
C2 GPIO1 Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 1. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
C3 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
C4
C5
C6
C7
C8
C9
D1 I2C_SDA1 Digital I/O Digital core I/O and control pins Digital input I2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
D10 GPIO2 Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 2. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
D11 PP_5V0 Power High-current power pins 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
D2 I2C_SCL1 Digital I/O Digital core I/O and control pins Digital input I2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
D3 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
D4
D5 DEBUG_CTL2
(GPIO17, I2C ADDR B5)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 17. At power-up, pin state is sensed to determine bit 5 of the I2C address.
D6 HRESET Digital I/O Digital core I/O and control pins Hi-Z Active high hardware reset input. Will re-load settings from external flash memory. Ground pin when HRESET functionality is not used.
D7 GPIO7 Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 7. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
D8 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
D9 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
E1 LDO_BMC Power Low-current power pins Output of the USB-PD BMC transceiver output level LDO. Bypass with capacitance CLDO_BMC to GND.
E10 GPIO5
(HPD RX)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 5. Can be configured as Hot Plug Detect (HPD) RX when DisplayPort mode supported. Must be tied high or low through a 1-kΩ pullup or pulldown resistor when used as a configuration input. Ground pin with a 1-MΩ resistor when unused in the application.
E11 MRESET
(GPIO11)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 11. Forces RESETZ to assert. By default, this pin asserts RESETZ when pulled high. The pin can be programmed to assert RESETZ when pulled low. Ground pin with a 1MΩ resistor when unused in the application.
E2 UART_TX Digital output Port multiplexer pins UART_RX UART serial transmit data. Connect pin to another TPS65982 UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65982.
E3 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
E4 DEBUG_CTL1
(GPIO16, I2C ADDR B4)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 16. At power-up, pin state is sensed to determine bit 4 of the I2C address.
E5 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
E6
E7
E8
E9 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
F1 I2C_ADDR Analog I/O Digital core I/O and control pins Analog input Sets the I2C address for both I2C ports as well as determine the master and slave devices for memory code sharing.
F10 BUSPOWERZ
(GPIO10)
Analog Input Digital core I/O and control pins Input (Hi-Z) General purpose digital I/O 10. Sampled by ADC at boot. Tie pin to LDO_3V3 through a 100-kΩ resistor to disable PP_HV and PP_EXT power paths during dead-battery or no-battery boot conditions. Refer to the BUSPOWERZ table for more details.
F11 RESETZ
(GPIO9)
Digital I/O Digital core I/O and control pins Push-pull output (Low) General purpose digital I/O 9. Active-low reset output when VOUT_3V3 is low (driven low on start-up). Float pin when unused.
F2 UART_RX Digital input Port multiplexer pins Digital input UART serial receive data. Connect pin to another TPS65982 UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65982 and ground pin through a 100-kΩ resistance.
F3 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
F4 SWD_DATA Digital I/O Port multiplexer pins Resistive pull high SWD serial data. Float pin when unused.
F5 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
F6
F7
F8
F9 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
G1 LDO_3V3 Power Low-current power pins Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND.
G10 GPIO6 Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 6. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
G11 GPIO3 Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 3. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
G2 R_OSC Analog I/O Digital core I/O and control pins Hi-Z External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC.
G3 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
G4 SWD_CLK Digital input Port multiplexer pins Resistive pull high SWD serial clock. Float pin when unused.
G5 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
G6
G7
G8
G9 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
H1 VIN_3V3 Power Low-current power pins Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
H10 PP_CABLE Power High-current power pins 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused.
H11 VBUS Power High-current power pins 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
H2 VOUT_3V3 Power Low-current power pins Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND. Float pin when unused.
H3 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
H4 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
H5
H6 GPIO8 Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 8. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
H7 SS Analog output External HV-FET control and sense pins and soft start Driven low Soft Start. Tie pin to capacitance CSS to ground.
H8 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
H9 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
J1 AUX_P Analog I/O Port multiplexer pins Hi-Z System-side DisplayPort connection to port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
J10 VBUS Power High-current power pins 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
J11
J2 AUX_N Analog I/O Port multiplexer pins Hi-Z System-side DisplayPort connection to port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
J3 No Ball Blank Ground and no connect pins Unpopulated ball for A1 marker and unpopulated inner ring.
J4
J5
J6
J7
J8
J9
K1 LDO_1V8A Power Low-current power pins Output of the 1.8-V LDO for core analog circuits. Bypass with capacitance CLDO_1V8A to GND.
K10 RPD_G2 Analog I/O Type-C port pins Hi-Z Tie pin to C_CC2 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
K11 VBUS Power High-current power pins 5-V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
K2 DEBUG2
(GPIO14)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 14. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
K3 DEBUG4
(GPIO12)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 12. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
K4 LSX_P2R Digital output Port multiplexer pins Hi-Z System side low speed RX to system from port. This pin is configurable to be an output from the digital core or the crossbar multiplexer from the port. Float pin when unused.
K5 USB_RP_N Analog I/O Port multiplexer pins Hi-Z System side USB2.0 high-speed connection to Port Multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
K6 C_USB_TP Analog I/O Type-C port pins Hi-Z Port-side top USB D+ connection to port multiplexer.
K7 C_USB_BP Analog I/O Type-C port pins Hi-Z Port-side bottom USB D+ connection to port multiplexer.
K8 C_SBU1 Analog I/O Type-C port pins Hi-Z Port-side Sideband Use connection of port multiplexer.
K9 RPD_G1 Analog I/O Type-C port pins Hi-Z Tie pin to C_CC1 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
L1 GND Ground Ground and no connect pins Ground. Connect all balls to ground plane.
L10 C_CC2 Analog I/O Type-C port pins Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2 to GND.
L11 NC Blank Ground and no connect pins Populated ball that must remain unconnected.
L2 DEBUG1
(GPIO15)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 15. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
L3 DEBUG3
(GPIO13)
Digital I/O Digital core I/O and control pins Hi-Z General purpose digital I/O 13. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
L4 LSX_R2P Digital input Port multiplexer pins Digital input System side low speed TX from system to port. This pin is configurable to be an input to the digital core or the crossbar multiplexer to the port. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
L5 USB_RP_P Analog I/O Port multiplexer pins Hi-Z System side USB2.0 high-speed connection to Port Multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
L6 C_USB_TN Analog I/O Type-C port pins Hi-Z Port-side top USB D– connection to port multiplexer.
L7 C_USB_BN Analog I/O Type-C port pins Hi-Z Port-side bottom USB D– connection to port multiplexer.
L8 C_SBU2 Analog I/O Type-C port pins Hi-Z Port-side Sideband Use connection of port multiplexer.
L9 C_CC1 Analog I/O Type-C port pins Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 to GND.