SLVSD02D March   2015  – June 2019 TPS65982

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Diagram
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Legend for Pinout Drawing
    2.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Requirements and Characteristics
    6. 7.6  Power Supervisor Characteristics
    7. 7.7  Power Consumption Characteristics
    8. 7.8  Cable Detection Characteristics
    9. 7.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 7.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 7.11 Port Power Switch Characteristics
    12. 7.12 Port Data Multiplexer Switching Characteristics
    13. 7.13 Port Data Multiplexer Clamp Characteristics
    14. 7.14 Port Data Multiplexer SBU Detection Characteristics
    15. 7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
    16. 7.16 Port Data Multiplexer USB Endpoint Characteristics
    17. 7.17 Port Data Multiplexer BC1.2 Detection Characteristics
    18. 7.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 7.19 Input/Output (I/O) Characteristics
    20. 7.20 I2C Slave Characteristics
    21. 7.21 SPI Master Characteristics
    22. 7.22 BUSPOWERZ Configuration Characteristics
    23. 7.23 Thermal Shutdown Characteristics
    24. 7.24 Oscillator Characteristics
    25. 7.25 Single-Wire Debugger (SWD) Timing Requirements
    26. 7.26 HPD Timing Requirements
    27. 7.27 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  USB-PD Physical Layer
        1. 9.3.1.1 USB-PD Encoding and Signaling
        2. 9.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.1.4 USB-PD BMC Transmitter
        5. 9.3.1.5 USB-PD BMC Receiver
      2. 9.3.2  Cable Plug and Orientation Detection
        1. 9.3.2.1 Configured as a DFP
        2. 9.3.2.2 Configured as a UFP
        3. 9.3.2.3 Dead-Battery or No-Battery Support
      3. 9.3.3  Port Power Switches
        1. 9.3.3.1  5V Power Delivery
        2. 9.3.3.2  5V Power Switch as a Source
        3. 9.3.3.3  PP_5V0 Current Sense
        4. 9.3.3.4  PP_5V0 Current Limit
        5. 9.3.3.5  Internal HV Power Delivery
        6. 9.3.3.6  Internal HV Power Switch as a Source
        7. 9.3.3.7  Internal HV Power Switch as a Sink
        8. 9.3.3.8  Internal HV Power Switch Current Sense
        9. 9.3.3.9  Internal HV Power Switch Current Limit
        10. 9.3.3.10 External HV Power Delivery
        11. 9.3.3.11 External HV Power Switch as a Source with RSENSE
        12. 9.3.3.12 External HV Power Switch as a Sink with RSENSE
        13. 9.3.3.13 External HV Power Switch as a Sink without RSENSE
        14. 9.3.3.14 External Current Sense
        15. 9.3.3.15 External Current Limit
        16. 9.3.3.16 Soft Start
        17. 9.3.3.17 BUSPOWERZ
        18. 9.3.3.18 Voltage Transitions on VBUS through Port Power Switches
        19. 9.3.3.19 HV Transition to PP_RV0 Pull-Down on VBUS
        20. 9.3.3.20 VBUS Transition to VSAFE0V
        21. 9.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery
        22. 9.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        23. 9.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 9.3.4  USB Type-C Port Data Multiplexer
        1. 9.3.4.1  USB Top and Bottom Ports
        2. 9.3.4.2  Multiplexer Connection Orientation
        3. 9.3.4.3  Digital Crossbar Multiplexer
        4. 9.3.4.4  SBU Crossbar Multiplexer
        5. 9.3.4.5  Signal Monitoring and Pullup/Pulldown
        6. 9.3.4.6  Port Multiplexer Clamp
        7. 9.3.4.7  USB2.0 Low-Speed Endpoint
        8. 9.3.4.8  Battery Charger (BC1.2) Detection Block
        9. 9.3.4.9  BC1.2 Data Contact Detect
        10. 9.3.4.10 BC1.2 Primary and Secondary Detection
      5. 9.3.5  Power Management
        1. 9.3.5.1 Power-On and Supervisory Functions
        2. 9.3.5.2 Supply Switch-Over
        3. 9.3.5.3 RESETZ and MRESET
      6. 9.3.6  Digital Core
      7. 9.3.7  USB-PD BMC Modem Interface
      8. 9.3.8  System Glue Logic
      9. 9.3.9  Power Reset Congrol Module (PRCM)
      10. 9.3.10 Interrupt Monitor
      11. 9.3.11 ADC Sense
      12. 9.3.12 UART
      13. 9.3.13 I2C Slave
      14. 9.3.14 SPI Master
      15. 9.3.15 Single-Wire Debugger Interface
      16. 9.3.16 DisplayPort HPD Timers
      17. 9.3.17 ADC
        1. 9.3.17.1 ADC Divider Ratios
        2. 9.3.17.2 ADC Operating Modes
        3. 9.3.17.3 Single Channel Readout
        4. 9.3.17.4 Round Robin Automatic Readout
        5. 9.3.17.5 One Time Automatic Readout
      18. 9.3.18 I/O Buffers
        1. 9.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 9.3.18.2 IOBUF_OD
        3. 9.3.18.3 IOBUF_UTX
        4. 9.3.18.4 IOBUF_URX
        5. 9.3.18.5 IOBUF_PORT
        6. 9.3.18.6 IOBUF_I2C
        7. 9.3.18.7 IOBUF_GPIOHSPI
        8. 9.3.18.8 IOBUF_GPIOHSSWD
      19. 9.3.19 Thermal Shutdown
      20. 9.3.20 Oscillators
    4. 9.4 Device Functional Modes
      1. 9.4.1 Boot Code
      2. 9.4.2 Initialization
      3. 9.4.3 I2C Configuration
      4. 9.4.4 Dead-Battery Condition
      5. 9.4.5 Application Code
      6. 9.4.6 Flash Memory Read
      7. 9.4.7 Invalid Flash Memory
      8. 9.4.8 UART Download
    5. 9.5 Programming
      1. 9.5.1 SPI Master Interface
      2. 9.5.2 I2C Slave Interface
        1. 9.5.2.1 I2C Interface Description
        2. 9.5.2.2 I2C Clock Stretching
        3. 9.5.2.3 I2C Address Setting
        4. 9.5.2.4 Unique Address Interface
        5. 9.5.2.5 I2C Pin Address Setting
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Fully-Featured USB Type-C and PD Charger Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 External FET Path Components (PP_EXT and RSENSE)
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 TPS65982 External Flash
          2. 10.2.1.2.2 I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD) Resistors
          3. 10.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 10.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 10.2.1.2.5 Soft Start (SS) Capacitor
          6. 10.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), and Sideband-Use (SBU) Connections
          7. 10.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors
          8. 10.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          9. 10.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 Source Power Delivery Profiles for Type-C Ports
          2. 10.2.2.1.2 Sink Power Delivery Profile for Type-C Ports
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 TPS65982 and System Controller Interaction
          2. 10.2.2.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 10.2.2.2.3 9.3.2.3 DC Barrel Jack and Type-C PD Charging
          4. 10.2.2.2.4 Primary TPS65982 Flash Master and Secondary Port
          5. 10.2.2.2.5 TPS65982 Dead Battery Support Primary and Secondary Port
          6. 10.2.2.2.6 Debugging Methods
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 3.3-V Power
      1. 11.1.1 VIN_3V3 Input Switch
      2. 11.1.2 VOUT_3V3 Output Switch
      3. 11.1.3 VBUS 3.3-V LDO
    2. 11.2 1.8 V Core Power
      1. 11.2.1 1.8 V Digital LDO
      2. 11.2.2 1.8 V Analog LDO
    3. 11.3 VDDIO
      1. 11.3.1 Recommended Supply Load Capacitance
      2. 11.3.2 Schottky for Current Surge Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  TPS65982 Recommended Footprints
        1. 12.1.1.1 Standard TPS65982 Footprint (Circular Pads)
      2. 12.1.2  Alternate TPS65982 Footprint (Oval Pads)
      3. 12.1.3  Top TPS65982 Placement and Bottom Component Placement and Layout
      4. 12.1.4  Oval Pad Footprint Layout and Placement
      5. 12.1.5  Component Placement
      6. 12.1.6  Designs Rules and Guidance
      7. 12.1.7  Routing PP_HV, PP_EXT, PP_5V0, and VBUS
      8. 12.1.8  Routing Top and Bottom Passive Components
      9. 12.1.9  Void Via Placement
      10. 12.1.10 Top Layer Routing
      11. 12.1.11 Inner Signal Layer Routing
      12. 12.1.12 Bottom Layer Routing
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Port Power Switch Characteristics

Recommended operating conditions; TA = –10 to 85°C unless otherwise noted
PARAMETER TEST CONDITIONS(3) MIN TYP MAX UNIT
RPPCC PP_CABLE to C_CCn power switch resistance 312
RPP5V PP_5V0 to VBUS power switch resistance 50 60
RPPHV PP_HV to VBUS power switch resistance 95 135
IHVACT Active quiescent current from PP_HV pin, EN_HV = 1 1 mA
IHVSD Shutdown quiescent current from PP_HV pin, EN_HV = 0 100 μA
IHVEXTACT Active quiescent current from SENSEP pin, EN_HV = 1 Configured as source 1 mA
Active quiescent current from VBUS pin, EN_HV = 1 Configured as sink 3.5 mA
IHVEXTSD Shutdown quiescent current from SENSEP pin, EN_HV = 0 40 μA
IPP5VACT Active quiescent current from PP_5V0 1 mA
IPP5VSD Shutdown quiescent current from PP_5V0 100 μA
ILIMHV(5) PP_HV current limit, setting 0 1.007 1.118 1.330 A
PP_HV current limit, setting 1 1.258 1.398 1.638 A
PP_HV current limit, setting 2 1.51 1.678 1.945 A
PP_HV current limit, setting 3 1.761 1.957 2.153 A
PP_HV current limit, setting 4 2.013 2.237 2.46 A
PP_HV current limit, setting 5 2.265 2.516 2.768 A
PP_HV current limit, setting 6 2.516 2.796 3.076 A
PP_HV current limit, setting 7 2.768 3.076 3.383 A
PP_HV current limit, setting 8 3.02 3.355 3.691 A
PP_HV current limit, setting 9 3.271 3.635 3.998 A
PP_HV current limit, setting 10 3.523 3.914 4.306 A
PP_HV current limit, setting 11 3.775 4.194 4.613 A
PP_HV current limit, setting 12 4.026 4.474 4.921 A
PP_HV current limit, setting 13 4.278 4.753 5.228 A
PP_HV current limit, setting 14 4.529 5.033 5.536 A
PP_HV current limit, setting 15 5.033 5.592 6.151 A
ILIMHVEXT(4)(5) PP_EXT current limit, setting 0 0.986 1.12 1.254 A
PP_EXT current limit, setting 1 1.231 1.399 1.567 A
PP_EXT current limit, setting 2 1.477 1.678 1.879 A
PP_EXT current limit, setting 3 1.761 1.957 2.153 A
PP_EXT current limit, setting 4 2.012 2.236 2.46 A
PP_EXT current limit, setting 5 2.263 2.515 2.767 A
PP_EXT current limit, setting 6 2.514 2.794 3.074 A
PP_EXT current limit, setting 7 2.765 3.073 3.381 A
PP_EXT current limit, setting 8 3.016 3.352 3.688 A
PP_EXT current limit, setting 9 3.267 3.631 3.995 A
PP_EXT current limit, setting 10 3.519 3.91 4.301 A
PP_EXT current limit, setting 11 3.77 4.189 4.608 A
PP_EXT current limit, setting 12 4.021 4.468 4.915 A
PP_EXT current limit, setting 13 4.272 4.747 5.222 A
PP_EXT current limit, setting 14 4.523 5.026 5.529 A
PP_EXT current limit, setting 15 5.025 5.584 6.143 A
ILIMPP5V(5) PP_5V0 current limit, setting 0 1.006 1.118 1.330 A
PP_5V0 current limit, setting 1 1.132 1.258 1.484 A
PP_5V0 current limit, setting 2 1.258 1.398 1.638 A
PP_5V0 current limit, setting 3 1.384 1.538 1.691 A
PP_5V0 current limit, setting 4 1.51 1.677 1.845 A
PP_5V0 current limit, setting 5 1.636 1.817 1.999 A
PP_5V0 current limit, setting 6 1.761 1.957 2.153 A
PP_5V0 current limit, setting 7 1.887 2.097 2.307 A
PP_5V0 current limit, setting 8 2.013 2.237 2.46 A
PP_5V0 current limit, setting 9 2.139 2.376 2.614 A
PP_5V0 current limit, setting 10 2.265 2.516 2.768 A
PP_5V0 current limit, setting 11 2.39 2.656 2.922 A
PP_5V0 current limit, setting 12 2.516 2.796 3.075 A
PP_5V0 current limit, setting 13 2.642 2.936 3.229 A
PP_5V0 current limit, setting 14 2.768 3.075 3.383 A
PP_5V0 current limit, setting 15 3.019 3.355 3.69 A
ILIMPPCC PP_CABLE current limit (highest setting) 0.6 0.75 0.9 A
PP_CABLE current limit (lowest setting) 0.35 0.45 0.55 A
IHV_ACC(1) PP_HV current sense accuracy  I = 100 mA Reverse current blocking disabled 3.25 5 6.75 A/V
 I = 200 mA 4 5 6 A/V
 I = 500 mA 4.4 5 5.6 A/V
 I ≥ 1 A 4.5 5 5.5 A/V
IHVEXT_ACC PP_EXT current sense accuracy (excluding RSENSE accuracy)  I = 100 mA , RSENSE = 10 mΩ Reverse current blocking disabled 3.5 5 6.5 A/V
 I = 200 mA, RSENSE = 10 mΩ 4 5 6 A/V
 I = 500 mA, RSENSE = 10 mΩ 4.4 5 5.6 A/V
 I ≥ 1 A, RSENSE = 10 mΩ 4.5 5 5.5 A/V
IPP5V_ACC(1) PP_5V0 current sense accuracy  I = 100 mA Reverse current blocking disabled 1.95 3 4.05 A/V
 I = 200 mA 2.4 3 3.6 A/V
 I = 500 mA 2.64 3 3.36 A/V
 I ≥ 1 A 2.7 3 3.3 A/V
IPPCBL_ACC PP_CABLE current sense accuracy  I = 100 mA 1 A/V
 I = 200 mA 1 A/V
 I = 500 mA 1 A/V
IGATEEXT(2) External Gate Drive Current on HV_GATE1 and HV_GATE2 4 5 6 μA
VGSEXT VGS voltage driving external FETs 4.5 7.5 V
TON_HV PP_HV path turn on time from enable to VBUS = 95% of PP_HV voltage Configured as a source or as a sink with soft start disabled. PP_HV = 20 V, CVBUS = 10 μF, ILOAD = 100 mA 8 ms
TON_5V PP_5V0 path turn on time from enable to VBUS = 95% of PP_5V0 voltage Configured as a source or as a sink with soft start disabled. PP_5V0 = 5 V, CVBUS = 10 μF, ILOAD = 100 mA 2.5 ms
TON_CC PP_CABLE path turn on time from enable to C_CCn = 95% of the PP_CABLE voltage PP_CABLE = 5 V, C_CCn = 500 nF, ILOAD = 100 mA 2 ms
ISS Soft start charging current 5.5 7 8.5 μA
RSS_DIS Soft start discharge resistance 0.6 1 1.4
VTHSS Soft start complete threshold 1.35 1.5 1.65 V
TSSDONE Soft start complete time CSS = 220 nF 31.9 46.2 60.5 ms
VREVPHV Reverse current blocking voltage threshold for PP_HV switch 2 6 10 mV
VREVPEXT Reverse Current Blocking voltage Threshold for PP_EXT external switches 2 6 10 mV
VREV5V0 Reverse current blocking voltage threshold for PP_5V0 switches 2 6 10 mV
VHVDISPD Voltage threshold above VIN at which the pulldown RHVDISPD on VBUS will disable during a transition from PHV to 5V0 45 200 250 mV
VSAFE0V Voltage that is a safe 0 V per USB-PD Specifications 0 0.8 V
TSAFE0V Voltage transition time to VSAFE0V 650 ms
VSO_HV Voltage on PP_HV or PP_HVEXT above which the PP_HV or PP_EXT to PP_5V0 transition on VBUS will meet transition requirements 9.9 V
SRPOS Maximum slew rate for positive voltage transitions 0.03 V/μs
SRNEG Maximum slew rate for negative voltage transitions –0.03 V/μs
TSTABLE EN to stable time for both positive and negative voltage transitions 275 ms
VSRCVALID Supply output tolerance beyond VSRCNEW during time TSTABLE –0.5 0.5 V
VSRCNEW Supply output tolerance –5 5 %
The current sense in the ADC will not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV because of the reverse blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.
Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ω to provide adequate response time to short circuit events.
Maximum capacitance on VBUS when configured as a source must not exceed 12 µF.
Specified for a 10-mΩ RSENSE resistor and 10-mΩ RSENSE application code setting. Values will scale with a different RSENSE resistance and application code setting.
Settings selected automatically by application code for the current limit needed in the application.