SLVSD13C October   2015  – August 2016 TPS65986

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Power Consumption Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 6.11 Port Power Switch Characteristics
    12. 6.12 Port Data Multiplexer Switching and Timing Characteristics
    13. 6.13 Port Data Multiplexer Clamp Characteristics
    14. 6.14 Port Data Multiplexer SBU Detection Requirements
    15. 6.15 Port Data Multiplexer Signal Monitoring Pull-up and Pull-down Characteristics
    16. 6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 6.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 6.19 Input/Output (I/O) Requirements and Characteristics
    20. 6.20 I2C Slave Requirements and Characteristics
    21. 6.21 SPI Master Characteristics
    22. 6.22 Single-Wire Debugger (SWD) Timing Requirements
    23. 6.23 BUSPOWERZ Configuration Requirements
    24. 6.24 HPD Timing Requirements and Characteristics
    25. 6.25 Thermal Shutdown Characteristics
    26. 6.26 Oscillator Requirements and Characteristics
    27. 6.27 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Cable Plug and Orientation Detection
        1. 8.3.2.1 Configured as a DFP
        2. 8.3.2.2 Configured as a UFP
        3. 8.3.2.3 Dead-Battery or No-Battery Support
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1  5V Power Delivery
        2. 8.3.3.2  5V Power Switch as a Source
        3. 8.3.3.3  PP_5V0 Current Sense
        4. 8.3.3.4  PP_5V0 Current Limit
        5. 8.3.3.5  Internal HV Power Delivery
        6. 8.3.3.6  Internal HV Power Switch as a Source
        7. 8.3.3.7  Internal HV Power Switch as a Sink
        8. 8.3.3.8  Internal HV Power Switch Current Sense
        9. 8.3.3.9  Internal HV Power Switch Current Limit
        10. 8.3.3.10 Soft Start
        11. 8.3.3.11 BUSPOWERZ
        12. 8.3.3.12 Voltage Transitions on VBUS through Port Power Switches
        13. 8.3.3.13 HV Transition to PP_RV0 Pull-down on VBUS
        14. 8.3.3.14 VBUS Transition to VSAFE0V
        15. 8.3.3.15 C_CC1 and C_CC2 Power Configuration and Power Delivery
        16. 8.3.3.16 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        17. 8.3.3.17 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 8.3.4  USB Type-C Port Data Multiplexer
        1. 8.3.4.1  USB Top and Bottom Ports
        2. 8.3.4.2  Multiplexer Connection Orientation
        3. 8.3.4.3  Digital Crossbar Multiplexer
        4. 8.3.4.4  SBU Crossbar Multiplexer
        5. 8.3.4.5  Signal Monitoring and Pull-up/Pull-down
        6. 8.3.4.6  Port Multiplexer Clamp
        7. 8.3.4.7  USB2.0 Low-Speed Endpoint
        8. 8.3.4.8  Battery Charger (BC1.2) Detection Block
        9. 8.3.4.9  BC1.2 Data Contact Detect
        10. 8.3.4.10 BC1.2 Primary and Secondary Detection
      5. 8.3.5  Power Management
        1. 8.3.5.1 Power-On and Supervisory Functions
        2. 8.3.5.2 Supply Switch-Over
        3. 8.3.5.3 RESETZ and MRESET
      6. 8.3.6  Digital Core
      7. 8.3.7  USB-PD BMC Modem Interface
      8. 8.3.8  System Glue Logic
      9. 8.3.9  Power Reset Congrol Module (PRCM)
      10. 8.3.10 Interrupt Monitor
      11. 8.3.11 ADC Sense
      12. 8.3.12 UART
      13. 8.3.13 I2C Slave
      14. 8.3.14 SPI Master
      15. 8.3.15 Single-Wire Debugger Interface
      16. 8.3.16 DisplayPort HPD Timers
      17. 8.3.17 ADC
        1. 8.3.17.1 ADC Divider Ratios
        2. 8.3.17.2 ADC Operating Modes
        3. 8.3.17.3 Single Channel Readout
        4. 8.3.17.4 Round Robin Automatic Readout
        5. 8.3.17.5 One Time Automatic Readout
      18. 8.3.18 I/O Buffers
        1. 8.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 8.3.18.2 IOBUF_OD
        3. 8.3.18.3 IOBUF_UTX
        4. 8.3.18.4 IOBUF_URX
        5. 8.3.18.5 IOBUF_PORT
        6. 8.3.18.6 IOBUF_I2C
        7. 8.3.18.7 IOBUF_GPIOHSPI
        8. 8.3.18.8 IOBUF_GPIOHSSWD
      19. 8.3.19 Thermal Shutdown
      20. 8.3.20 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Dead-Battery Condition
      5. 8.4.5 Application Code
      6. 8.4.6 Flash Memory Read
      7. 8.4.7 Invalid Flash Memory
      8. 8.4.8 UART Download
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. 8.5.2.1 I2C Interface Description
        2. 8.5.2.2 I2C Clock Stretching
        3. 8.5.2.3 I2C Address Setting
        4. 8.5.2.4 Unique Address Interface
        5. 8.5.2.5 I2C Pin Address Setting
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB Type-C and PD Dongle Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 TPS65986 External Flash
          2. 9.2.1.2.2 I2C, Debug Control (DEBUG_CTL), and SPI Resistors
          3. 9.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 9.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 9.2.1.2.5 Soft Start (SS) Capacitor
          6. 9.2.1.2.6 Port Power Switch (PP_HV and PP_5V0) Capacitors
          7. 9.2.1.2.7 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          8. 9.2.1.2.8 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 9.2.1.3 Application Curves
      2. 9.2.2 USB Type-C and PD Dock Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. 9.2.2.2.2 TPS65986 Primary and Secondary Interaction
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 TPS65986 and System Controller Interaction
          2. 9.2.3.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 9.2.3.2.3 DC Barrel Jack and Type-C PD Charging
          4. 9.2.3.2.4 Primary TPS65986 Flash Master and Secondary Port
          5. 9.2.3.2.5 TPS65986 Dead Battery Support Primary and Secondary Port
          6. 9.2.3.2.6 Debugging Methods
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 VBUS 3.3-V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
      2. 10.3.2 Schottky for Current Surge Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  TPS65986 Recommended Footprints
        1. 11.1.1.1 Standard TPS65986 Footprint (Circular Pads)
      2. 11.1.2  Alternate TPS65986 Footprint (Oval Pads)
      3. 11.1.3  Top TPS65986 Placement and Bottom Component Placement and Layout
      4. 11.1.4  Oval Pad Footprint Layout and Placement
      5. 11.1.5  Component Placement
      6. 11.1.6  Designs Rules and Guidance
      7. 11.1.7  Routing PP_HV, PP_5V0, and VBUS
      8. 11.1.8  Routing Top and Bottom Passive Components
      9. 11.1.9  Void Via Placement
      10. 11.1.10 Top Layer Routing
      11. 11.1.11 Inner Signal Layer Routing
      12. 11.1.12 Bottom Layer Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Development Support
      2. 12.1.2 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The typical applications of the TPS65986 include chargers, notebooks, tablets, ultrabooks, docks, dongles, and any other product supporting USB Type-C and/or USB-PD as a power source, power sink, data DFP, data UFP, or dual-role port (DRP). The typical applications outlined in the following sections detail the TPS65986 used in a USB Type-C and PD Dongle Application, a USB Type-C and PD Dock Application, and a Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort.

9.2 Typical Application

9.2.1 USB Type-C and PD Dongle Application

The TPS65986 controls two separate power paths making it a flexible option for Type C PD dongle application that simultaneously charges a USB PD DisplayPort video source (for example, a notebook computer). The dongle application of the TPS65986, shown in Figure 74, directly connects a barrel jack power supply to the PP_HV pins and uses a GPIO to sense when a barrel jack is present. The TPS65986 will automatically enable a Source PDO to charge the notebook connected at the Type-C port and initiate a Power Role Swap PD message if the notebook was connected to the dongle first. When the laptop is connected first and the barrel jack is not present, the dongle will boot from VBUS in No Battery mode and provide power to VIN_3V3, the Type-A USB3 receptacle, and the video receptacle. Refer to Figure 75 for a timing diagram showing the dongle behavior when it is bus-powered from the notebook and Figure 76 for a timing diagram when the dongle is line-powered from the barrel jack. Figure 77 shows the VBUS hand-off when the barrel jack becomes present after the notebook and then the barrel jack is removed abruptly. The video receptacle can be DisplayPort, HDMI, or VGA although only DisplayPort is shown in Figure 74. The dongle application uses a Type-C plug which makes it a captive cable. As a result, the CC1 pin of the TPS65986 can be directly routed to CC at the plug and the SuperSpeed signal pairs for USB3 data and DisplayPort video can be routed directly to the respective plugs at the opposite end of the dongle.

TPS65986 fig_65986_9_Typ_App_3_Dongle_Application.gif Figure 74. Type-C and PD Dongle Application

9.2.1.1 Design Requirements

For a USB Type-C and PD dongle application, Table 11 shows the input/output voltage requirements and expected current capabilities for the TPS65986.

Table 11. Dongle Application Design Parameters

DESIGN PARAMETER EXAMPLE VALUE DIRECTION OF CURRENT
PP_5V0 Input Voltage and Current Capabilities 5 V, 3 A Sourcing to VBUS
PP_HV Input/Output Voltage and Current Capabilities 5V, 3 A/20 V, 3 A Sinking/Sourcing from/to VBUS
VIN_3V3 Voltage and Current Requirements 2.85 V - 3.45 V, 50 mA Internal TPS65986 Circuitry

9.2.1.2 Detailed Design Procedure

The passive components required for the TPS65986 to operate in this application are outlined in the following sections. For more details on the comparator circuit used for barrel jack detection, refer to DC Barrel Jack and Type-C PD Charging.

9.2.1.2.1 TPS65986 External Flash

The external flash (not shown in Figure 74) is mandatory and contains the TPS65986 application firmware and must be sized to 256-kB minimum. The recommended flash used is the W25Q80 is a 1-MB size flash operating at 3.3 V and is powered from the LDO_3V3 output of the TPS65986.

9.2.1.2.2 I2C, Debug Control (DEBUG_CTL), and SPI Resistors

The DEBUG_CTL1/2 pins must be tied to LDO_3V3 through a pull-up resistor for current-limiting. Pull-up resistors on the I2C_CLK, I2C_SDA, and I2C_IRQZ are used for debugging purposes. In most simple dongle designs, I2C communication is not needed. 3.3-kΩ pull-up resistors from SPI_SSZ and SPI_MISO to LDO_3V3 must also be used for SPI Read/Write stability and a header should be connected to I2C and SPI pins for debugging purposes.

9.2.1.2.3 Oscillator (R_OSC) Resistor

A 15-kΩ 0.1% resistor is needed for key PD BMC communication timing and the USB2.0 endpoint. A 1% 15-kΩ resistor is not recommended to be used because the internal oscillators will not be controlled well enough by this loose resistor tolerance.

9.2.1.2.4 VBUS Capacitor and Ferrite Bead

A 1uF ceramic capacitor is placed close to the TPS65986 VBUS pins. A 6-A ferrite bead is used in this design along with four high frequency noise 10-nF capacitors placed close to the Type-C connector to minimize noise.

9.2.1.2.5 Soft Start (SS) Capacitor

The recommended 0.22 µF is placed on the TPS65986 SS pin.

9.2.1.2.6 Port Power Switch (PP_HV and PP_5V0) Capacitors

The PP_HV path is capable of supporting up to 3 A which will require additional capacitance to support system loading by the device connected to the dongle. A ceramic 10 µF (X7R/X5R) capacitor, coupled with a 0.1 µF high frequency capacitor, is placed close to the TPS65986.

The PP_5V0 supply requires a ceramic 4.7-µF (X7R/X5R) capacitor, coupled with a 0.1-µF high-frequency capacitor, is placed close to the TPS65986. The PP_5V0 path can support 3 A.

9.2.1.2.7 Cable Connection (CCn) Capacitors and RPD_Gn Connections

To support Dead Battery or No Battery mode, RPD_G1 and RPD_G2 must be shorted to CC1 and CC2, respectively. The CC1 and CC2 lines require a 220-pF capacitor to GND to filter out high frequency noise while passing USB PD BMC communication. In a dongle design that uses a Type-C plug to perform as a captive cable, only RPD_G1 and CC1 must be routed while RPD_G2 may be shorted to GND and CC2 can be left floating.

9.2.1.2.8 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO

For all capacitances it is important to factor in DC voltage de-rating of ceramic capacitors. Generally the effective capacitance is halved with voltage applied.

VIN_3V3 is connected to VDDIO which ensures that the I/Os of the TPS65986’s will be configured to 3.3 V. A 1 µF capacitor is used and is shared between VDDIO and VIN_3V3. LDO_1V8D, LDO_1V8A, and LDO_BMC each have their own 1 µF capacitor. In this design LDO_3V3 powers the TPS65986’s external flash and various pull ups. A 10 µF capacitor was chosen to support these additional connections. VOUT_3V3 is not used in this design and capacitor is not needed.

9.2.1.3 Application Curves

TPS65986 fig_65986_9_Typ_App_3_Dongle_Timing1_Bus-Powered.gif Figure 75. Bus-Powered TPS65986 Dongle Application Timing Diagram
TPS65986 fig_65986_9_Typ_App_3_Dongle_Timing3_VBUS-handoff.gif Figure 77. TPS65986 Dongle Application VBUS Hand-Off Timing Diagram
TPS65986 fig_65986_9_Typ_App_3_Dongle_Timing2_Line-Powered.gif Figure 76. Line-Powered TPS65986 Dongle Application Timing Diagram

9.2.2 USB Type-C and PD Dock Application

The TPS65986 controls two separate power paths making it a flexible option for Type-C and PD dock application that simultaneously charges a USB PD DisplayPort video source (for example, a notebook computer). The dock application of the TPS65986, shown in Figure 78, uses a common node for PP_HV of both TPS65986 devices and uses a GPIO to sense when a charger is present on the charger-side TPS65986. The host-side TPS65986 will automatically enable a Source PDO to charge the notebook connected at the Type-C port and initiate a Power Role Swap PD message if the laptop was connected to the dock first. When the notebook is connected first and the charger is not present, the dock will boot from VBUS in No Battery mode and provide power to VIN_3V3, the Type-A USB3 receptacle, the video receptacle, and support circuitry. Refer to Figure 79 for a timing diagram showing the dock behavior when it is bus-powered from the host-side and Figure 80 for a timing diagram when the dock is line-powered from the charger-side. In the timing diagrams, the host -side is referred to as the Left (L) side and the charger-side is referred to as the Right (R) side, the same orientation shown in the Figure 78 block diagram. The video receptacle can be DisplayPort, HDMI, or VGA although only DisplayPort is shown in Figure 78. The dock application uses a Type-C receptacle and an HD3SS460 SuperSpeed multiplexer which is controlled by the host-side TPS65986. The CC1/2 pins of the TPS65986 will detect cable orientation and automatically configure the HD3SS460 SuperSpeed signal pairs for 2-lanes of USB3 data and 2-lanes of DisplayPort video or 4-lanes of DisplayPort video depending on the Alternate Mode configured by the host.

TPS65986 fig_65986_9_Typ_App_4_Dock_Application.gif Figure 78. Type-C and PD Dock Application

9.2.2.1 Design Requirements

For a USB Type-C and PD dock application, Table 12 shows the input/output voltage requirements and expected current capabilities for the TPS65986.

Table 12. Dock Application Design Parameters

DESIGN PARAMETER EXAMPLE VALUE DIRECTION OF CURRENT
PP_5V0 Input Voltage and Current Capabilities 5 V, 3 A Sourcing to VBUS
PP_HV Input/Output Voltage and Current Capabilities 5V, 3A/12-20 V, <3 A Sinking/Sourcing from/to VBUS of Host side TPS65986
PP_HV Input Voltage and Current Capabilities 12-20 V, 3 A Sinking from VBUS of Charger side TPS65986
VIN_3V3 Voltage and Current Requirements 2.85 - 3.45 V, 100 mA (50 mA each) Internal TPS65986 Circuitry

9.2.2.2 Detailed Design Procedure

The same passive components used in the USB Type-C and PD Dongle Application are also applicable in this design to support all of the features of the TPS65986. Additional design information is provided below for additional passive components required and to explain the UART interaction of the two TPS65986 devices. The TPS65986 control of the HD3SS460 SuperSpeed multiplexer is explained in HD3SS460 Control and DisplayPort Configuration, while the details of a Primary and Secondary TPS65986 sharing a single SPI flash are explained in Primary TPS65986 Flash Master and Secondary Port.

9.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors

The PP_5V0 and PP_CABLE supplies are connected together therefore a ceramic 22-µF (X7R/X5R) capacitor coupled with a 0.1-µF high-frequency capacitor must be placed close to the host-side TPS65986. The PP_5V0 path can support 3 A and the PP_CABLE path supports 600 mA for active Type C cables.

9.2.2.2.2 TPS65986 Primary and Secondary Interaction

The host-side TPS65986 is the primary device which loads application code from Flash memory via a direct SPI connection, while the charger-side TPS65986 is the secondary device which loads application code over UART from the primary. After loading application code, the secondary TPS65986 controls the primary TPS65986 over UART when a Type-C charger is connected by copying the Active Sink PDO of the secondary into the Source PDO of the primary while accounting for current losses used to provide power to the dock system circuitry. An output GPIO of the secondary, GPIOy, connected to an input GPIO of the primary, GPIOx, to indicate that line power is present and initiate a Power Role swap if the system was initially bus-powered. More complex docking systems which are additionally powered by a barrel jack may require a I2C master system controller to control both TPS65986 devices via the I2C slave port.

9.2.2.3 Application Curves

TPS65986 fig_65986_9_Typ_App_4_Dock_Timing1_Left.gif Figure 79. Bus-Powered TPS65986 Dock Application Timing Diagram
TPS65986 fig_65986_9_Typ_App_4_Dock_Timing2_Right.gif Figure 80. Line-Powered TPS65986 Dock Application Timing Diagram

9.2.3 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort

The TPS65986 features support for DisplayPort over Type-C Alternate Mode and manages sinking and sourcing of power in Power Delivery. This application applies to both a tablet and a notebook computer with two fully-featured USB Type-C ports. The block diagram, shown in Figure 81, depicts a two port system that is capable of charging from either Type C port over PD and entering DisplayPort Alternate Mode for video. With the DisplayPort support, the TPS65986 controls an external SuperSpeed multiplexer, HD3SS460, to route the appropriate super-speed and SBU signals to the Type-C connector. The HD3SS460 is controlled through GPIOs configured by the TPS65986 application code and the HD3SS460 is designed to meet the timing requirements defined by the DisplayPort over Type-C specification. A system controller is also necessary to handle some of the dynamic aspects of Power Delivery such as reducing power capabilities when system battery power is low. Audio accessory device is supported by the design as well.

TPS65986 fig_65986_9_Typ_App_2_Dual_Port_Notebook_Application.gif Figure 81. Dual-Port Notebook Application

9.2.3.1 Design Requirements

For a dual-port tablet or notebook application, Table 13 Design Parameters shows the input voltage requirements and expected current capabilities.

Table 13. Dual-Port Notebook Application Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE DIRECTION OF CURRENT
PP_5V0 Input Voltage and Current Capabilities 5 V, 3 A Sourcing to VBUS
PP_CABLE Input Voltage and Current Capabilities 5 V, 500 mA Sourcing to VCONN
PP_HV Input/Output Voltage and Current Capabilities 12 V - 20 V, 3A/20 V, 3 A Sinking from VBUS
VIN_3V3 Voltage and Current Requirements 2.85 V - 3.45 V, 50 mA Internal TPS65986 Circuitry

9.2.3.2 Detailed Design Procedure

The same passive components used in the USB Type-C and PD Dock Application are also applicable in this design to support all of the features of the TPS65986. Additional design information is provided below to explain the connections between the TPS65986 and the system controller and the TPS65986 and the HD3SS460 SuperSpeed multiplexer.

9.2.3.2.1 TPS65986 and System Controller Interaction

The TPS65986 features an I2C slave port, where the system controller has the ability to write to the I2C slave port. The I2C port has an I2C interrupt that will inform the system controller that a change has happened in the system. This allows the system controller to dynamically budget power and reconfigures a port’s capabilities dependent on current state of the system. The system controller is also used for updating the TPS65986 firmware over I2C, where the Operating System loads the Firmware update to the system controller and then the system controller updates the firmware stored in the SPI Flash via I2C writes to the TPS65986.

9.2.3.2.2 HD3SS460 Control and DisplayPort Configuration

The two Type-C ports in this design support DisplayPort simultaneously on both ports. When a system is not capable of supporting video on both ports the system controller will disable DisplayPort on the second Type-C port through I2C. Table 14 below shows the DisplayPort configurations supported in the system. Table 15 shows the summary of the TPS65986 GPIO signals control for the HD3SS460. The HD3SS460 is also capable of multiplexing the required signals to the SBU_1/2 pins.

Table 14. Supported DisplayPort Configurations

DisplayPort Role Display Port
Pin Assignment
DisplayPort Lanes
Configuration 1 DFP_D Pin Assignment C 4 Lane
Configuration 2 DFP_D Pin Assignment D 2 Lane and USB 3.1
Configuration 3 DFP_D Pin Assignment E 4 Lane (Dongle Support)

Table 15. TPS65986 and HD3SS460 GPIO Control

TPS65986 GPIO HD3SS460 Control Pin Description
GPIO0 AMSEL Alternate Mode Selection (DP/USB3)
GPIO3 EN Super Speed Multiplexer Enable
DEBUG2 POL Type-C Cable Orientation

9.2.3.2.3 DC Barrel Jack and Type-C PD Charging

The system is design to either charge over Type-C or from the DC barrel jack. The TPS65986 detects that the DC barrel jack is connected to GPIOn. In the simplest form, a voltage divider could be set to the GPIO I/O level when the DC Barrel jack voltage is present, as shown in Figure 82. A comparator circuit is recommend and used in this design for design robustness, as shown in Figure 83.

TPS65986 fig_65982_9_Typ_App_DC_Barrel_Jack_Voltage_Divider_v2.gif Figure 82. DC Barrel Jack Voltage Divider
TPS65986 fig_65982_9_Typ_App_DC_Barrel_Jack_Detect_Comparator_v2.gif Figure 83. Barrel Jack Detect Comparator

This detect signal is used to determine if the barrel jack is present to support the 20 V PD power contracts and to hand-off charging from barrel jack to Type-C or Type-C to barrel jack. When the DC barrel jack is detected the TPS6986 at each Type-C port will not request 20 V for charging and the system will be able to support a 20 V source power contract to another device. When the DC Barrel Jack is disconnected the TPS65986 will exit any 20 V source power contract and re-negotiate a power contract. When the DC Barrel Jack is connected the TPS65986 will send updated source capabilities and re-negotiate a power contract if needed.

The PFET enable will be controlled by the DC barrel jack detect comparator depicted in Figure 83. This will allow the system to power up from dead battery through the barrel jack as well as the Type-C ports. The example uses back-to-back PFETs for disabling and enabling the power path for the DC Barrel Jack. It is important to use PFETs that are rated above the specified parameters to ensure robustness of the system. The DC Barrel Jack voltage in this design is assumed to be 20 V at 5 A, so the PFETs are recommended to be rated at a minimum of 30 V and 10 A of current.

The TPS65986 in this design also provides the GPIO control for the PFET gate drive that passes the DC Barrel Jack Voltage to the system.

9.2.3.2.4 Primary TPS65986 Flash Master and Secondary Port

A single flash can be used for two TPS65986’s in a system where the primary TPS65986 is connected to the flash and the secondary TPS65986 is connected to the primary through UART. UART data is used to pass the firmware from the primary TPS65986 to the secondary TPS65986 in the system. Figure 84 shows a simplified block diagram of how a primary and secondary TPS65986 are connected using a single flash. The primary TPS65986 must have its I2C_ADDR pin tied to GND with a 0Ω to denote it as the primary TPS65986.

TPS65986 fig_65986_9_Typ_App_Primary_and_Secondary_Single_Flash_v2.gif Figure 84. Primary and Secondary TPS65986 Sharing a Single Flash

9.2.3.2.5 TPS65986 Dead Battery Support Primary and Secondary Port

The TP65982 supports dead battery functionality to be able to power up from the Type-C port. This design supports dead battery using the PP_HV path, where RPD_G1/2 and CC1/2 are connected respectively, and BUSPOWERZ is connected to LDO_1V8D to path 5 V VBUS into the system through the PP_HV path. The TPS65986 will soft-start the PP_HV path in order to comply with USB2.0 inrush current requirements. In order to enable PD functionality the TPS65986 must boot the application firmware from the flash. For the primary TPS65986, once VBUS is detected at 5 V it will automatically start to load the application firmware from the flash. The TPS65986 will then be able communicate over PD and establish a power contract at the required 20 V. Figure 85 shows the boot up sequence of the primary TPS65986.

When the TPS65986 that is not connected to the flash is connected in dead battery it will pass the 5 V from VBUS in to the battery charger where the battery would be able to generate the needed System 3.3 V rail to both of the TPS65986 devices. Once the primary TPS65986 has a valid 3.3 V supply (VBUS = 0 V on Primary TPS65986) it will load the application firmware from the flash and pass it to the secondary TPS65986 that is connected. Once the secondary TPS65986 has loaded the application firmware over UART it will be able to negotiate a 20 V power contract. Figure 86 shows the dead battery sequence of the secondary TPS65986.

9.2.3.2.6 Debugging Methods

The TPS65986 has methods of debugging a Type-C and PD system. Additional series resistors are used for debugging. The I2C channel allows a designer to check the system state through the Host Interface Specification. By attaching 0-Ω series resistors between the I2C master and the TPS65986 and additionally adding 0-Ω series resistors between the TPS65986 and test points, a multi-master scenario can be avoided. This allows breaking the connection between the I2C channel and the system to allow I2C access to the TPS65986 from an external tool. A header is used to allow for connections without soldering; however, SMT test pads can be used to provide a place to solder “blue-wires” for testing.

Exposing the SWD_DATA and SWD_CLK pins will allow for more advanced debugging if needed. A header or SMT test point is also used for the SWD_DATA and SWD_CLK pins.

9.2.3.3 Application Curves

TPS65986 fig_65986_9_Typ_App_Primary_Dead_Battery_Timing.gif Figure 85. Primary TPS65986 Dead Battery Sequence
TPS65986 fig_65986_9_Typ_App_Secondary_Dead_Battery_Timing.gif Figure 86. Secondary TPS65986 Dead Battery Sequence