SLVSD13C October   2015  – August 2016 TPS65986

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Power Consumption Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 6.11 Port Power Switch Characteristics
    12. 6.12 Port Data Multiplexer Switching and Timing Characteristics
    13. 6.13 Port Data Multiplexer Clamp Characteristics
    14. 6.14 Port Data Multiplexer SBU Detection Requirements
    15. 6.15 Port Data Multiplexer Signal Monitoring Pull-up and Pull-down Characteristics
    16. 6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 6.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 6.19 Input/Output (I/O) Requirements and Characteristics
    20. 6.20 I2C Slave Requirements and Characteristics
    21. 6.21 SPI Master Characteristics
    22. 6.22 Single-Wire Debugger (SWD) Timing Requirements
    23. 6.23 BUSPOWERZ Configuration Requirements
    24. 6.24 HPD Timing Requirements and Characteristics
    25. 6.25 Thermal Shutdown Characteristics
    26. 6.26 Oscillator Requirements and Characteristics
    27. 6.27 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Cable Plug and Orientation Detection
        1. 8.3.2.1 Configured as a DFP
        2. 8.3.2.2 Configured as a UFP
        3. 8.3.2.3 Dead-Battery or No-Battery Support
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1  5V Power Delivery
        2. 8.3.3.2  5V Power Switch as a Source
        3. 8.3.3.3  PP_5V0 Current Sense
        4. 8.3.3.4  PP_5V0 Current Limit
        5. 8.3.3.5  Internal HV Power Delivery
        6. 8.3.3.6  Internal HV Power Switch as a Source
        7. 8.3.3.7  Internal HV Power Switch as a Sink
        8. 8.3.3.8  Internal HV Power Switch Current Sense
        9. 8.3.3.9  Internal HV Power Switch Current Limit
        10. 8.3.3.10 Soft Start
        11. 8.3.3.11 BUSPOWERZ
        12. 8.3.3.12 Voltage Transitions on VBUS through Port Power Switches
        13. 8.3.3.13 HV Transition to PP_RV0 Pull-down on VBUS
        14. 8.3.3.14 VBUS Transition to VSAFE0V
        15. 8.3.3.15 C_CC1 and C_CC2 Power Configuration and Power Delivery
        16. 8.3.3.16 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        17. 8.3.3.17 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 8.3.4  USB Type-C Port Data Multiplexer
        1. 8.3.4.1  USB Top and Bottom Ports
        2. 8.3.4.2  Multiplexer Connection Orientation
        3. 8.3.4.3  Digital Crossbar Multiplexer
        4. 8.3.4.4  SBU Crossbar Multiplexer
        5. 8.3.4.5  Signal Monitoring and Pull-up/Pull-down
        6. 8.3.4.6  Port Multiplexer Clamp
        7. 8.3.4.7  USB2.0 Low-Speed Endpoint
        8. 8.3.4.8  Battery Charger (BC1.2) Detection Block
        9. 8.3.4.9  BC1.2 Data Contact Detect
        10. 8.3.4.10 BC1.2 Primary and Secondary Detection
      5. 8.3.5  Power Management
        1. 8.3.5.1 Power-On and Supervisory Functions
        2. 8.3.5.2 Supply Switch-Over
        3. 8.3.5.3 RESETZ and MRESET
      6. 8.3.6  Digital Core
      7. 8.3.7  USB-PD BMC Modem Interface
      8. 8.3.8  System Glue Logic
      9. 8.3.9  Power Reset Congrol Module (PRCM)
      10. 8.3.10 Interrupt Monitor
      11. 8.3.11 ADC Sense
      12. 8.3.12 UART
      13. 8.3.13 I2C Slave
      14. 8.3.14 SPI Master
      15. 8.3.15 Single-Wire Debugger Interface
      16. 8.3.16 DisplayPort HPD Timers
      17. 8.3.17 ADC
        1. 8.3.17.1 ADC Divider Ratios
        2. 8.3.17.2 ADC Operating Modes
        3. 8.3.17.3 Single Channel Readout
        4. 8.3.17.4 Round Robin Automatic Readout
        5. 8.3.17.5 One Time Automatic Readout
      18. 8.3.18 I/O Buffers
        1. 8.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 8.3.18.2 IOBUF_OD
        3. 8.3.18.3 IOBUF_UTX
        4. 8.3.18.4 IOBUF_URX
        5. 8.3.18.5 IOBUF_PORT
        6. 8.3.18.6 IOBUF_I2C
        7. 8.3.18.7 IOBUF_GPIOHSPI
        8. 8.3.18.8 IOBUF_GPIOHSSWD
      19. 8.3.19 Thermal Shutdown
      20. 8.3.20 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Dead-Battery Condition
      5. 8.4.5 Application Code
      6. 8.4.6 Flash Memory Read
      7. 8.4.7 Invalid Flash Memory
      8. 8.4.8 UART Download
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. 8.5.2.1 I2C Interface Description
        2. 8.5.2.2 I2C Clock Stretching
        3. 8.5.2.3 I2C Address Setting
        4. 8.5.2.4 Unique Address Interface
        5. 8.5.2.5 I2C Pin Address Setting
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB Type-C and PD Dongle Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 TPS65986 External Flash
          2. 9.2.1.2.2 I2C, Debug Control (DEBUG_CTL), and SPI Resistors
          3. 9.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 9.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 9.2.1.2.5 Soft Start (SS) Capacitor
          6. 9.2.1.2.6 Port Power Switch (PP_HV and PP_5V0) Capacitors
          7. 9.2.1.2.7 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          8. 9.2.1.2.8 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 9.2.1.3 Application Curves
      2. 9.2.2 USB Type-C and PD Dock Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. 9.2.2.2.2 TPS65986 Primary and Secondary Interaction
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 TPS65986 and System Controller Interaction
          2. 9.2.3.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 9.2.3.2.3 DC Barrel Jack and Type-C PD Charging
          4. 9.2.3.2.4 Primary TPS65986 Flash Master and Secondary Port
          5. 9.2.3.2.5 TPS65986 Dead Battery Support Primary and Secondary Port
          6. 9.2.3.2.6 Debugging Methods
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 VBUS 3.3-V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
      2. 10.3.2 Schottky for Current Surge Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  TPS65986 Recommended Footprints
        1. 11.1.1.1 Standard TPS65986 Footprint (Circular Pads)
      2. 11.1.2  Alternate TPS65986 Footprint (Oval Pads)
      3. 11.1.3  Top TPS65986 Placement and Bottom Component Placement and Layout
      4. 11.1.4  Oval Pad Footprint Layout and Placement
      5. 11.1.5  Component Placement
      6. 11.1.6  Designs Rules and Guidance
      7. 11.1.7  Routing PP_HV, PP_5V0, and VBUS
      8. 11.1.8  Routing Top and Bottom Passive Components
      9. 11.1.9  Void Via Placement
      10. 11.1.10 Top Layer Routing
      11. 11.1.11 Inner Signal Layer Routing
      12. 11.1.12 Bottom Layer Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Development Support
      2. 12.1.2 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

8 Detailed Description

8.1 Overview

The TPS65986 is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and orientation detection for a USB Type-C and PD plug or receptacle. The TPS65986 communicates with the cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port power switches, controls an external high current port power switch, and multiplexes high-speed data to the port for USB2.0 and supported Alternate Mode sideband information. The TPS65986 also controls an attached super-speed multiplexer to simultaneously support USB3.0/3.1 data rates and DisplayPort video.

The TPS65986 is divided into six main sections: the USB-PD controller, the cable plug and orientation detection circuitry, the port power switches, the port data multiplexer, the power management circuitry, and the digital core.

The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data is output through either the C_CC1 pin or the C_CC2 pin, depending on the orientation of the reversible USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and more detailed circuitry, refer to the USB-PD Physical Layer section.

The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and orientation detection, a description of its features and more detailed circuitry, refer to the Cable Plug and Orientation Detection section.

The port power switches provide power to the system port through the VBUS pin and also through the C_CC1 or C_CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a description of its features and more detailed circuitry, refer to the Port Power Switches section.

The port data multiplexer connects various input pairs to the system port through the C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU1 and C_SBU2 pins. For a high-level block diagram of the port data multiplexer, a description of its features and more detailed circuitry, refer to the USB Type-C Port Data Multiplexer section.

The power management circuitry receives and provides power to the TPS65986 internal circuitry and to the VOUT_3V3 and LDO_3V3 outputs. For a high-level block diagram of the power management circuitry, a description of its features and more detailed circuitry, refer to the Power Management section.

The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as handling control of all other TPS65986 functionality. A small portion of the digital core contains non-volatile memory, called boot code, which is capable of initializing the TPS65986 and loading a larger, configurable portion of application code into volatile memory in the digital core. For a high-level block diagram of the digital core, a description of its features and more detailed circuitry, refer to the Digital Core section.

The digital core of the TPS65986 also interprets and uses information provided by the analog-to-digital converter ADC (see the ADC section), is configurable to read the status of general purpose inputs and trigger events accordingly, and controls general outputs which are configurable as push-pull or open-drain types with integrated pull-up or pull-down resistors and can operate tied to a 1.8 V or 3.3 V rail. The TPS65986 is an I2C slave to be controlled by a host processor (see the I2C Slave Interface section), an SPI master to write to and read from an external flash memory (see the SPI Master Interface section), and is programmed by a single-wire debugger (SWD) connection (see the Single-Wire Debugger Interface section).

The TPS65986 also integrates a thermal shutdown mechanism (see Thermal Shutdown section) and runs off of accurate clocks provided by the integrated oscillators (see the Oscillators section).

8.2 Functional Block Diagram

TPS65986 fig_65986_8p2_FBD_main_source_v3.gif

8.3 Feature Description

8.3.1 USB-PD Physical Layer

Figure 10 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and orientation detection block.

TPS65986 fig_65982_8p2_FBD_USBPD_phy_and_plug_detection.gif Figure 10. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry

USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output on the same pin (C_CC1 or C_CC2) that is DC biased due to the DFP (or UFP) cable attach mechanism discussed in the Cable Plug and Orientation Detection section.

8.3.1.1 USB-PD Encoding and Signaling

Figure 11 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 12 illustrates the high-level block diagram of the baseband USB-PD receiver.

TPS65986 fig_65982_8p2_FBD_usbpd_bmc_transmit.gif Figure 11. USB-PD Baseband Transmitter Block Diagram
TPS65986 fig_65982_8p2_FBD_usbpd_bmc_receive.gif Figure 12. USB-PD Baseband Receiver Block Diagram

The USB-PD baseband signal is driven on the C_CCn pins with a tri-state driver. The tri-state driver is slew rate limited to reduce the high frequency components imparted on the cable and to avoid interference with frequencies used for communication.

8.3.1.2 USB-PD Bi-Phase Marked Coding

The USBP-PD physical layer implemented in the TPS65986 is compliant to the USB-PD Specifications. The encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity (limited to ½ bit over an arbitrary packet, so a very low DC level). Figure 13 illustrates Biphase Mark Coding.

TPS65986 fig_65982_8p2_FBD_usbpd_bmc_data_example.gif Figure 13. Biphase Mark Coding Example

The USB PD baseband signal is driven onto the C_CC1 or C_CC2 pins with a tri-state driver. The tri-state driver is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending the USB-PD preamble, the transmitter will start by transmitting a low level. The receiver at the other end will tolerate the loss of the first edge. The transmitter will terminate the final bit by an edge to ensure the receiver clocks the final bit of EOP.

8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks

The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal edge at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate that will have minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the rise and fall times. Refer to the USB-PD Specifications for more details.

8.3.1.4 USB-PD BMC Transmitter

The TPS65986 transmits and receives USB-PD data over one of the C_CCn pins. The C_CCn pin is also used to determine the cable orientation (see the Cable Plug and Orientation Detection section) and maintain cable/device attach detection. Thus, a DC bias will exist on the C_CCn. The transmitter driver will overdrive the C_CCn DC bias while transmitting, but will return to a Hi-Z state allowing the DC voltage to return to the C_CCn pin when not transmitting. Figure 14 shows the USB-PD BMC TX/Rx driver block diagram.

TPS65986 fig_65982_8p2_FBD_usbpd_bmc_txrx_driver.gif Figure 14. USB-PD BMC TX/Rx Block Diagram

Figure 15 shows the transmission of the BMC data on top of the DC bias. Note that the DC bias can be anywhere between the minimum threshold for detecting a UFP attach (VD_CCH_USB) and the maximum threshold for detecting a UFP attach to a DFP (VD_CCH_3P0) defined in the Cable Plug and Orientation Detection section. This means that the DC bias can be below VOH of the transmitter driver or above VOH.

TPS65986 fig_65982_8p2_FBD_usbpd_bmc_dcoffset.gif Figure 15. TX Driver Transmission with DC Bias

The transmitter drives a digital signal onto the C_CCn lines. The signal peak VTXP is adjustable by application code and sets the VOH/VOL for the BMC data that is transmitted, and is defined in USB-PD TX Driver Voltage Adjustment Parameter. Keep in mind that the settings in a final system must meet the TX masks defined in the USB-PD Specifications.

When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by the driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the noise ingression in the cable.

Figure 16 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is bounded.

ZDRVER is defined by Equation 1.

Equation 1. TPS65986 Eq1_zdriver_slvsd02.gif
TPS65986 fig_65982_8p2_FBD_usbpd_bmc_zdriver.gif Figure 16. ZDRIVER Circuit

8.3.1.5 USB-PD BMC Receiver

The receiver block of the TPS65986 receives a signal that falls within the allowed Rx masks defined in the USB PD specification. The receive thresholds and hysteresis come from this mask. The values for VRXTR and VRXTF are listed in USB-PD Baseband Signal Requirements and Characteristics.

Figure 17 shows an example of a multi-drop USB-PD connection. This connection has the typical UFP (device) to DFP (host) connection, but also includes cable USB-PD TX/Rx blocks. Only one system can be transmitting at a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach detection.

TPS65986 fig_65982_8p2_FBD_usbpd_bmc_full_connection.gif Figure 17. Example USB-PD Multi-Drop Configuration

8.3.2 Cable Plug and Orientation Detection

Figure 18 shows the plug and orientation detection block at each C_CC pin (C_CC1 and C_CC2). Each pin has identical detection circuitry.

TPS65986 fig_65982_8p2_FBD_plug_orientation_and_detection_block.gif Figure 18. Plug and Orientation Detection Block

8.3.2.1 Configured as a DFP

When configured as a DFP, the TPS65986 detects when a cable or a UFP is attached using the C_CC1 and C_CC2 pins. When in a disconnected state, the TPS65986 monitors the voltages on these pins to determine what, if anything, is connected. See the USB Type-C Specification for more information.

Table 1 shows the high-level detection results. Refer to the USB Type-C Specification for more information.

Table 1. Cable Detect States for a DFP

C_CC1 C_CC2 CONNECTION STATE RESULTING ACTION
Open Open Nothing attached Continue monitoring both C_CC pins for attach. Power is not applied to VBUS or VCONN until a UFP connect is detected.
Rd Open UFP attached Monitor C_CC1 for detach. Power is applied to VBUS but not to VCONN (C_CC2).
Open Rd UFP attached Monitor C_CC2 for detach. Power is applied to VBUS but not to VCONN (C_CC1).
Ra Open Powered Cable/No UFP attached Monitor C_CC2 for a UFP attach and C_CC1 for cable detach. Power is not applied to VBUS or VCONN (C_CC1) until a UFP attach is detected.
Open Ra Powered Cable/No UFP attached Monitor C_CC1 for a UFP attach and C_CC2 for cable detach. Power is not applied to VBUS or VCONN (C_CC1) until a UFP attach is detected.
Ra Rd Powered Cable/UFP Attached Provide power on VBUS and VCONN (C_CC1) then monitor C_CC2 for a UFP detach. C_CC1 is not monitored for a detach.
Rd Ra Powered Cable/UFP attached Provide power on VBUS and VCONN (C_CC2) then monitor C_CC1 for a UFP detach. C_CC2 is not monitored for a detach.
Rd Rd Debug Accessory Mode attached Sense either C_CC pin for detach.
Ra Ra Audio Adapter Accessory Mode attached Sense either C_CC pin for detach.

When the TPS65986 is configured as a DFP, a current IH_CC is driven out each C_CCn pin and each pin is monitored for different states. When a UFP is attached to the pin, a pull-down resistance of Rd to GND will exist. The current IH_CC is then forced across the resistance Rd generating a voltage at the C_CCn pin.

When configured as a DFP advertising Default USB current sourcing capability, the TPS65986 applies IH_CC_USB to each C_CCn pin. When a UFP with a pull-down resistance Rd is attached, the voltage on the C_CCn pin will pull below VH_CCD_USB. The TPS65986 can also be configured as a DFP to advertise default (500 mA), 1.5 A and 3 A sourcing capabilities.

When the C_CCn pin is connected to an active cable VCONN (power to the active cable), the pull-down resistance will be different (Ra). In this case, the voltage on the C_CCn pin will pull below VH_CCA_USB/1P5/3P0 and the system will recognize the active cable.

The VH_CCD_USB/1P5/3P0 thresholds are monitored to detect a disconnection from each of these cases respectively. When a connection has been recognized and the voltage on the C_CCn pin rises above the VH_CCD_USB/1P5/3P0 threshold, the system will register a disconnection.

8.3.2.2 Configured as a UFP

When the TPS65986 is configured as a UFP, the TPS65986 presents a pull-down resistance RD_CC on each C_CCn pin and waits for a DFP to attach and pull-up the voltage on the pin. The DFP will pull-up the C_CC pin by applying either a resistance or a current. The UFP detects an attachment by the presence of VBUS. The UFP determines the advertised current from the DFP by the pull-up resistor applied to the C_CCn pin.

8.3.2.3 Dead-Battery or No-Battery Support

Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source will provide a voltage on VBUS. The TPS65986 is hardware-configurable to present this Rd during a dead-battery or no-battery condition. Additional circuitry provides a mechanism to turn off this Rd when the port is acting as a source. Figure 19 shows the RPD_Gn pin used to configure the behavior of the C_CCn pins, and elaborates on the basic cable plug and orientation detection block shown in Figure 18. RPD_G1 and RPD_G2 configure C_CC1 and C_CC2 respectively. A resistance R_RPD is connected to the gate of the pull-down FET on each C_CCn pin. This resistance must be pin-strapped externally in order to configure the C_CCn pin to behave in one of two ways: present an Rd pull-down resistance or present a Hi-Z when the TPS65986 is unpowered. During normal operation, RD will be RD_CC; however, while dead-battery or no-battery conditions exist, the resistance is un-trimmed and will be RD_DB. When RD_DB is presented during dead-battery or no-battery, application code will switch to RD_CC.

TPS65986 fig_65982_8p3_Features_C_CCn_and_RPD_Gn_pins.gif Figure 19. C_CCn and RPD_Gn pins

When C_CC1 is shorted to RPD_G1 and C_CC2 is shorted to RPD_G2 in an application of the TPS65986, booting from dead-battery or no-battery conditions will be supported. In this case, the gate driver for the pull-down FET is Hi-Z at its output. When an external connection pulls up on C_CCn (the case when connected to a DFP advertising with a pull-up resistance Rp or pull-up current), the connection through R_RPD will pull up on the FET gate turning on the pull-down through RD_DB. In this condition, the C_CCn pin will act as a clamp VTH_DB in series with the resistance RD_DB.

When RPD_G1 and RPD_G2 are shorted to GND in an application and not electrically connected to C_C1 and C_CC2, booting from dead-battery or no-battery conditions is not possible. In this case, the TPS65986 will present a Hi-Z on the C_CC1 and C_CC2 pins and a USB Type-C source will never provide a voltage on VBUS.

8.3.3 Port Power Switches

Figure 20 shows the TPS65986 port power path including all internal and external paths. The port power path provides to VBUS from PP_5V0, provides power to or from VBUS from or to PP_HV, and provides power from PP_CABLE to C_CC1 or C_CC2. The PP_CABLE to C_CCn switches shown in Figure 20 are the same as in Figure 10, but are now shown without the analog USB Type-C cable plug and orientation detection circuitry.

TPS65986 fig_65986_8p2_FBD_port_power_path_source.gif Figure 20. Port Power Paths

8.3.3.1 5V Power Delivery

The TPS65986 provides port power to VBUS from PP_5V0 when a low voltage output is needed. The switch path provides 5 V at up to 3 A to from PP_5V0 to VBUS. Figure 20 shows a simplified circuit for the switch from PP_5V0 to VBUS.

8.3.3.2 5V Power Switch as a Source

The PP_5V0 path is unidirectional, sourcing power from PP_5V0 to VBUS only. When the switch is on, the protection circuitry limits reverse current from VBUS to PP_5V0. Figure 21 shows the I-V characteristics of the reverse current protection feature. Figure 21 and the reverse current limit can be approximated using Equation 2.

Equation 2. IREV5V0 = VREV5V0/RPP5V
TPS65986 fig_65982_8p3_Features_pp5v0_source_diode_IV.gif Figure 21. 5 V Switch I-V Curve

8.3.3.3 PP_5V0 Current Sense

The current from PP_5V0 to VBUS is sensed through the switch and is available to be read digitally through the ADC.

8.3.3.4 PP_5V0 Current Limit

The current through PP_5V0 to VBUS is limited to ILIMPP5V and is controlled automatically by the digital core. When the current exceeds ILIMPP5V, the current-limit circuit activates. Depending on the severity of the over-current condition, the transient response will react in one of two ways: Figure 22 and Figure 23 show the approximate response time and clamping characteristics of the circuit for a hard short while Figure 24 shows the shows the approximate response time and clamping characteristics for a soft short with a load of 2 Ω.

TPS65986 D004_SLVSD02_TPS65982.gif Figure 22. PP_5V0 Current Limit with a Hard Short
TPS65986 D005_SLVSD02_TPS65982.gif Figure 23. PP_5V0 Current Limit with a Hard Short (Extended Time Base)
TPS65986 D006_SLVSD02_TPS65982.gif Figure 24. PP_5V0 Current Limit with a Soft Short (2 Ω)

8.3.3.5 Internal HV Power Delivery

The TPS65986 has an integrated, bi-directional high-voltage switch that is rated for up to 3 A of current. The TPS65986 is capable of sourcing or sinking high-voltage power through an internal switch path designed to support USB-PD power up to 20 V at 3 A of current. VBUS and PP_HV are both rated for up to 22 V as determined by Recommended Operating Conditions, and operate down to 0 V as determined by Absolute Maximum Ratings. In addition, VBUS is tolerant to voltages up to 22 V even when PP_HV is at 0 V. Similarly, PP_HV is tolerant up to 22 V while VBUS is at 0 V. The switch structure is designed to tolerate a constant operating voltage differential at either of these conditions. Figure 20 shows a simplified circuit for the switch from PP_HV to VBUS.

8.3.3.6 Internal HV Power Switch as a Source

The TPS65986 provides power from PP_HV to VBUS at the USB Type-C port as an output when operating as a source. When the switch is on as a source, the path behaves resistively until the current reaches the amount calculated by Equation 3 and then blocks reverse current from VBUS to PP_HV. Figure 25 shows the diode behavior of the switch as a source.

Equation 3. IREVHV = VREVHV/RPPHV
TPS65986 fig_65982_8p3_Features_pphv_source_diode_IV.gif Figure 25. Internal HV Switch I-V Curve as a Source

8.3.3.7 Internal HV Power Switch as a Sink

The TPS65986 can also receive power from VBUS to PP_HV when operating as a sink. When the switch is on as a sink the path behaves as an ideal diode and blocks reverse current from PP_HV to VBUS. Figure 26 shows the diode behavior of the switch as a sink.

TPS65986 fig_65982_8p3_Features_pphv_sink_diode_IV.gif Figure 26. Internal HV Switch I-V Curve as a Sink

8.3.3.8 Internal HV Power Switch Current Sense

The current from PP_HV to VBUS is sensed through the switch and is available to be read digitally through the ADC only when the switch is sourcing power. When sinking power, the readout from the ADC will not reflect the current.

8.3.3.9 Internal HV Power Switch Current Limit

The current through PP_HV to VBUS is current limited to ILIMPPHV (only when operating as a source) and is controlled automatically by the digital core. When the current exceeds ILIMPPHV, the current-limit circuit activates. Depending on the severity of the over-current condition, the transient response will react in one of two ways: Figure 27 shows the approximate response time and clamping characteristics of the circuit for a hard short while Figure 28 shows the approximate response time and clamping characteristics for a soft short of 7 Ω.

TPS65986 D007_SLVSD02_TPS65982.gif Figure 27. PP_HV Current Limit Response with a Hard Short
TPS65986 D008_SLVSD02_TPS65982.gif Figure 28. PP_HV Current Limit Response with a Soft Short (7 Ω)

8.3.3.10 Soft Start

When configured as a sink, the SS pin provides a soft start function for the high-voltage power path supply (PP_HV) up to 5.5 V. The soft start is enabled by application code or via the host processor. The SS pin is initially discharged through a resistance RSS_DIS. When the switch is turned on, a current ISS is sourced from the pin to a capacitance CSS. This current into the capacitance generates a slow ramping voltage. This voltage is sensed and the power path FETs turn on and the voltage follows this ramp. When the voltage reaches the threshold VTHSS, the power path FET will be near being fully turned on, the output voltage will be fully charged. At time TSSDONE, a signal to the digital core indicates that the soft start function has completed. The ramp rate of the supply is given by Equation 4:

Equation 4. TPS65986 Eq2_ramp_slvsd02.gif

The maximum ramp voltage for the supply is approximately 16.2 V. For any input voltage higher than this, the ramp will stop at 16.2 V until the firmware disables the soft start. At this point, the voltage will step to the input voltage at a ramp rate defined by approximately 7 μA into the gate capacitance of the switch. The TSSDONE time is independent of the actual final ramp voltage.

8.3.3.11 BUSPOWERZ

At power-up, when VIN_3V3 is not present and a dead-battery condition is supported as described in Dead-Battery or No-Battery Support, the TPS65986 will appear as a USB Type-C sink (device) causing a connected USB Type-C source (host) to provide 5 V on VBUS. The TPS65986 will power itself from the 5-V VBUS rail (see Power Management) and execute boot code (see Boot Code). The boot code will observe the BUSPOWERZ voltage, which will fall into one of two valid voltage ranges: VBPZ_DIS1/2 or VBPZ_HV (defined in BUSPOWERZ Configuration Requirements). These voltage ranges configure how the TPS65986 routes the 5 V present on VBUS to the system in a dead-battery or no-battery scenario.

When the voltage on BUSPOWERZ is in the VBPZ_DIS1/2 range (when BUSPOWERZ is tied to LDO_3V3 as in Figure 29 or BUSPOWERZ is shorted to GND), this indicates that the TPS65986 will not route the 5 V present on VBUS to the entire system. In this case, the TPS65986 will load SPI-connected flash memory and execute this application code. This configuration will disable both PP_HV high voltage switch and only use VBUS to power the TPS65986.

TPS65986 fig_65982_8p3_Features_buspowerz_disable.gif Figure 29. BUSPOWERZ Configured to Disable Power from VBUS

The BUSPOWERZ pin can alternately configure the TPS65986 to power the entire system through the PP_HV internal load switch when the voltage on BUSPOWERZ is in the VBPZ_HV range (when BUSPOWERZ is tied to LDO_1V8D as in Figure 30).

TPS65986 fig_65982_8p3_Features_buspowerz_pphv.gif Figure 30. BUSPOWERZ Configured with PP_HV as Input Power Path

8.3.3.12 Voltage Transitions on VBUS through Port Power Switches

Figure 31 shows the waveform for a positive voltage transition. The timing and voltages apply to both a transition from 0 V to PP_5V0 and a transition from PP_5V0 to PP_HV. When a switch is closed to transition the voltage, a maximum slew-rate of SRPOS occurs on the transition. The voltage ramp will remain monotonic until the voltage reaches VSRCVALID within the final voltage. The voltage may overshoot the new voltage by VSRCVALID. After time TSTABLE from the start of the transition, the voltage will fall to within VSRCNEW of the new voltage. During the time TSTABLE, the voltage may fall below the new voltage, but will remain within VSRCNEW of this voltage.

TPS65986 fig_65982_8p3_Features_VBUS_pos_voltage_transition.gif Figure 31. Positive Voltage Transition on VBUS

Figure 32 shows the waveform for a negative voltage transition. The timing and voltages apply to both a transition from PP_HV to PP_5V0 and a transition from PP_5V0 to 0V. When a switch is closed to transition the voltage, a maximum slew-rate of SRNEG occurs on the transition. The voltage ramp will remain monotonic until the voltage reaches TOLTRANUN within the final voltage. The voltage may overshoot the new voltage by TOLTRANLN. After time TSTABLE from the start of the transition, the voltage will fall to within VSRCNEW of the new voltage. During the time TSTABLE, the voltage may fall below the new voltage, but will remain within VSRCNEW of this voltage.

TPS65986 fig_65982_8p3_Features_VBUS_neg_voltage_transition.gif Figure 32. Negative Voltage Transition on VBUS

8.3.3.13 HV Transition to PP_RV0 Pull-down on VBUS

The TPS65986 has an integrated active pull-down on VBUS when transitioning from PP_HV to PP_5V0, shown in Figure 33. When the PP_HV switch is disabled and VBUS > PP_5V0 + VHVDISPD, amplifier turns on a current source and pulls down on VBUS. The amplifier implements active slew rate control by adjusting the pull-down current to prevent the slew rate from exceeding specification. When VBUS falls to within VHVDISPD of PP_5V0, the pull-down is turned off. The load on VBUS will then continue to pull VBUS down until the ideal diode switch structure turns on connecting it to PP_5V0. When switching from PP_HV to PP_5V0, PP_HV must be above VSO_HV to follow the switch-over shown in Figure 32.

TPS65986 fig_65982_8p3_Features_PP5V0_Slew_Rate_Control.gif Figure 33. PP_5V0 Slew Rate Control

8.3.3.14 VBUS Transition to VSAFE0V

When VBUS transitions to near 0 V (VSAFE0V), the pull-down circuit in Figure 33 is turned on until VBUS reaches VSAFE0V. This transition will occur within time TSAFE0V.

8.3.3.15 C_CC1 and C_CC2 Power Configuration and Power Delivery

The C_CC1 and C_CC2 pins are used to deliver power to active circuitry inside a connected cable and output USB-PD data to the cable and connected device. Figure 20 shows the C_CC1, and C_CC2 outputs to the port. Only one of these pins will be used to deliver power at a time depending on the cable orientation. The other pin will be used to transmit USB-PD data through the cable to a connected device.

Figure 34 shows a high-level flow of connecting these pins based on the cable orientation. See the Cable Plug and Orientation Detection section for more detailed information on plug and orientation detection.

TPS65986 fig_65982_8p3_Features_port_cc_and_vconn_flow.gif Figure 34. Port C_CC and VCONN Connection Flow

Figure 35 and Figure 36 show the two paths from PP_CABLE to the C_CCn pins. When one C_CCn pin is powered from PP_CABLE, the other is connected to the USB-PD BMC modem. The red line shows the power path and the green line shows the data path.

TPS65986 fig_65982_8p3_Features_port_cc_and_vconn_rightside_up_plug.gif Figure 35. Port C_CC1 and C_CC2 Normal Orientation Power from PP_CABLE
TPS65986 fig_65982_8p3_Features_port_cc_and_vconn_upside_down_plug.gif Figure 36. Port C_CC1 and C_CC2 Reverse Orientation Power from PP_CABLE

8.3.3.16 PP_CABLE to C_CC1 and C_CC2 Switch Architecture

Figure 20 shows the switch architecture for the PP_CABLE switch path to the C_CCc pins. Each path provides a unidirectional current from PP_CABLE to C_CC1 and C_CC2. The switch structure blocks reverse current from C_CC1 or C_CC2 to PP_CABLE.

8.3.3.17 PP_CABLE to C_CC1 and C_CC2 Current Limit

The PP_CABLE to C_CC1 and C_CC2 share current limiting through a single FET on the PP_CABLE side of the switch. The current limit ILIMPPCC is adjustable between two levels. When the current exceeds ILIMPPCC, the current-limit circuit activates. Depending on the severity of the over-current condition, the transient response will react in one of two ways: Figure 37 and Figure 38 show the approximate response time and clamping characteristics of the circuit for a hard short while Figure 39 shows the approximate response time and clamping characteristics for a soft short. The switch does not have reverse current blocking when the switch is enabled and current is flowing to either C_CC1 or C_CC2.

TPS65986 D009_SLVSD02_TPS65982.gif Figure 37. PP_CABLE to C_CCn Current Limit with a Hard Short
TPS65986 D010_SLVSD02_TPS65982.gif Figure 38. PP_CABLE to C_CCn Current Limit with a Hard Short (Extended Time Base)
TPS65986 D011_SLVSD02_TPS65982.gif Figure 39. PP_CABLE to C_CCn Current Limit Response with a Soft Short (2 Ω)

8.3.4 USB Type-C Port Data Multiplexer

The USB Type-C receptacle pin configuration is show in Figure 40. Not all signals shown are required for all platforms or devices. The basic functionality of the pins deliver USB 2.0 (D+ and D–) and USB 3.1 (TX and RX pairs) data buses, USB power (VBUS) and ground (GND). Configuration Channel signals (CC1 and CC2), and two Reserved for Future Use (SBU) signal pins. The data bus pins (Top and Bottom D+/D– and the SBU pins) are available to be used in non-USB applications as an Alternate Mode (i.e., DisplayPort, Thunderbolt™, etc.).

A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A11 A12
GND TX1+ TX1– VBUS CC1 D+ D– SBU1 VBUS RX2– RX2+ GND
GND RX1+ RX1– VBUS SBU2 D– D+ CC2 VBUS TX2– TX2+ GND
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
Figure 40. USB Type-C Receptacle Pin Configuration

The TPS65986 USB Type-C interface terminations are shown in Table 2. The outputs are determined based on detected cable orientation as well as the identified interface that is connected to the port. There are two USB output ports that may or may not be passing USB data. When an Alternate Mode is connected, these same ports may also pass that data (e.g. DisplayPort, Thunderbolt). Note, the TPS65986 pin to receptacle mapping is shown in Table 2. The super-speed RX and TX pairs are not mapped through the TPS65986 as this would place extra resistance and stubs on the super-speed lines and degrade signal performance. The SBU pair is not mapped through the TPS65986 and may be routed through an external multiplexer in the application.

Table 2. TPS65986 to USB Type-C Receptacle Mapping

DEVICE PIN Type-C RECEPTACLE PIN
VBUS VBUS (A4, A9, B4, B9)
C_CC1 CC1 (A5)
C_CC2 CC2 (B5)
C_USB_TP D+ (A6)
C_USB_TN D– (A7)
C_USB_BP D+ (B6)
C_USB_BN D– (B7)
C_SBU1 SBU1 (A8)
C_SBU2 SBU2 (B8)
TPS65986 fig_65986_8p2_FBD_port_muxes_stages.gif Figure 41. Port Data Multiplexers

Table 3 shows the typical signal types through the switch path. The UART_RX/TX path is digitally buffered to allow tri-state control for this path.

Table 3. Typical Signals through Analog Switch Path

INPUT PATH SIGNAL TYPE SIGNAL FUNCTION
UART_RX/TX Single Ended TX/Rx UART
AUX_P/N Differential DisplayPort and Thunderbolt AUX channel
USB_EP_P/N Differential USB 2.0 Low Speed Endpoint
USB_RP_P/N Differential USB 2.0 High Speed Data Root Port

8.3.4.1 USB Top and Bottom Ports

The Top (C_USB_TP and C_USB_TN) and Bottom (C_USB_BP and C_USB_BN) ports that correspond to the Type-C top and bottom USB D+/D– pairs are swapped based on the detected cable orientation. The symmetric pin order shown in Figure 40 from the A-side to the B-side allows the pins to connect to equivalent pins on the opposite side when the cable orientation is reversed.

8.3.4.2 Multiplexer Connection Orientation

Table 4 shows the multiplexer connection orientation. For the USB D+/D– pair top and bottom port connections, these connections are fixed. For the SBU port connections, the SBU crossbar multiplexer enables flipping of the signal pair and the connections shown are for the upside-up orientation. The CORE_UARTn connections come from a digital crossbar multiplexer that allows the UART_RX/TX to be mapped to any of the 1st stage multiplexers.

Table 4. Data Multiplexer Connections

SYSTEM PIN USB TOP PIN USB BOTTOM PIN SBU MULTIPLEXER PIN
USB_RP_P C_USB_TP C_USB_BP
USB_RP_N C_USB_TN C_USB_BN
USB_EP_P C_USB_TP C_USB_BP
USB_EP_N C_USB_TN C_USB_BN
AUX_P C_USB_TP C_USB_BP SBU1
AUX_N C_USB_TN C_USB_BN SBU2
CORE_UART0_TX C_USB_TP
CORE_UART0_RX C_USB_TN
CORE_UART1_TX C_USB_BP
CORE_UART1_RX C_USB_BN
CORE_UART2_TX SBU1
CORE_UART2_RX SBU2

8.3.4.3 Digital Crossbar Multiplexer

The TPS65986 UART path (UART_RX/TX pins) have digital inputs that pass through a cross-bar multiplexer inside the digital core. These pins are configurable as an input or output of the cross-bar multiplexer. The digital cross-bar multiplexer then connects to the port data multiplexers as shown in Figure 41. The connections are configurable via firmware. The default state at power-up is to connect a buffered version of UART_RX to UART_TX providing a bypass through the TPS65986 for daisy chaining during power on reset.

8.3.4.4 SBU Crossbar Multiplexer

The SBU Crossbar Multiplexer provides pins (C_SBU1 and C_SBU2) for future USB functionality as well as Alternate Modes. The multiplexer swaps the output pair orientation based on the cable orientation. For more information on Alternate Modes, refer to the USB PD Specification.

8.3.4.5 Signal Monitoring and Pull-up/Pull-down

The TPS65986 has comparators that may be enabled to interrupt the core when a switching event occurs on any of the port inputs. The input parameters for the detection are shown in Port Data Multiplexer Signal Monitoring Pull-up and Pull-down Characteristics. These comparators are disconnected by application code when these pins are not digital signals but an analog voltage.

The TPS65986 has pull-up and pull-down resistors between the first and second stage multiplexers of the port switch for each port output: C_SBU1/2, C_USB_TP/N, C_USB_BP/N. The configurable pull-up and pull-down resistance between each multiplexer are shown in Figure 42.

TPS65986 fig_65982_8p2_FBD_port_data_mux_rfu_detect.gif Figure 42. Port Detect and Pull-up/Pull-down

8.3.4.6 Port Multiplexer Clamp

Each input to the 2nd stage multiplexer is clamped to prevent voltages on the port from exceeding the safe operating voltage of circuits attached to the system side of the Port Data Multiplexer. Figure 43 shows the simplified clamping circuit. When a path through the 2nd stage multiplexer is closed, the clamp is connected to the one of the port pins (C_USB_TP/N, C_USB_BP/N, C_SBU1/2). When a path through the 2nd stage multiplexer is not closed, then the port pin is not clamped. As the pin voltage rises above the VCLMP_IND voltage, the clamping circuit activates, and sinks current to ground, preventing the voltage from rising further.

TPS65986 fig_65982_8p2_FBD_port_data_mux_clamp.gif Figure 43. Port Multiplexer Clamp

8.3.4.7 USB2.0 Low-Speed Endpoint

The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based accesses. The TPS65986 supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 bus to provide USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used for advertising the Billboard Class. When a host is connected to a device that provides Alternate Modes which cannot be supported by the host, the Billboard class allows a means for the host to report back to the user without any silent failures.

Figure 44 shows the USB Endpoint physical layer. The physical layer consists of the analog transceiver, the Serial Interface Engine, and the Endpoint FIFOs and supports low speed operation.

TPS65986 fig_65982_8p2_FBD_usb_ep_phy.gif Figure 44. USB Endpoint Phy

The transceiver is made up of a fully differential output driver, a differential to single-ended receive buffer and two single-ended receive buffers on the D+/D– independently. The output driver drives the D+/D– of the selected output of the Port Multiplexer. The signals pass through the 2nd Stage Port Data Multiplexer to the port pins. When driving, the signal is driven through a source resistance RS_EP. RS_EP is shown as a single resistor in USB Endpoint Phy but this resistance also includes the resistance of the 2nd Stage Port Data Multiplexer defined in Port Data Multiplexer Requirements and Characteristics. RPU_EP is disconnected during transmit mode of the transceiver.

When the endpoint is in receive mode, the resistance RPU_EP is connected to the D– pin of the top or bottom port (C_USB_TN or C_USB_BN) depending on the detected orientation of the cable. The RPU_EP resistance advertises low speed mode only.

8.3.4.8 Battery Charger (BC1.2) Detection Block

The battery charger (BC1.2) detection block integrates circuitry to detect when the connected entity on the USB D+/D– pins is a charger. To enable the required detection mechanisms, the block integrates various voltage sources, currents, and resistances to the Port Data Multiplexers. Figure 45 shows the connections of these elements to the Port Data Multiplexers.

TPS65986 fig_65982_8p2_FBD_BC1p2_block.gif Figure 45. BC1.2 Detection Circuitry

8.3.4.9 BC1.2 Data Contact Detect

Data Contact Detect follows the definition in the USB BC1.2 specification. The detection scheme sources a current IDP_SRC into the D+ pin of the USB connection. The current is sourced into either the C_USB_TP (top) or C_USB_BP (bottom) D+ pin based on the determined cable/device orientation. A resistance RDM_DWN is connected between the D– pin and GND. Again, this resistance is connected to either the C_USB_TN (top) or C_USB_BN (bottom) D– pin based on the determined cable/device orientation. The middle section of Figure 45, the current source IDP_SRC and the pull-down resistance RDM_DWN, is activated during data contact detection.

8.3.4.10 BC1.2 Primary and Secondary Detection

The Primary and Secondary Detection follow the USB BC1.2 specification. This detection scheme looks for a resistance between D+ and D– lines by forcing a known voltage on the first line, forcing a current sink on the second line and then reading the voltage on the second line using the general purpose ADC integrated in the TPS65986. To provide complete flexibility, 12 independent switches are connected to allow firmware to force voltage, sink current, and read voltage on any of the C_USB_TP, C_USB_TN, C_USB_BP, and C_USB_BN. The left and right sections of Figure 45, the voltage source VDX_SRC and the current source IDX_SNK, are activated during primary and secondary detection.

8.3.5 Power Management

The TPS65986 Power Management block receives power and generates voltages to provide power to the TPS65986 internal circuitry. These generated power rails are LDO_3V3, LDO_1V8A, and LDO_1V8D. LDO_3V3 is also a low power output to load flash memory. VOUT_3V3 is a low power output that does not power internal circuitry that is controlled by application code and can be used to power other ICs in some applications. The power supply path is shown in Figure 46.

TPS65986 fig_65982_8p2_FBD_power_supply_path.gif Figure 46. Power Supply Path

The TPS65986 is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. In this mode, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3 V circuitry and the 3.3 V I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V8D and LDO_1V8A to power the 1.8 V core digital circuitry and 1.8 V analog circuits. When VIN_3V3 power is unavailable and power is available on the VBUS, the TPS65986 will be powered from VBUS. In this mode, the voltage on VBUS is stepped down through an LDO to LDO_3V3. Switch S1 in Figure 46 is unidirectional and no current will flow from LDO_3V3 to VIN_3V3 or VOUT_3V3. When VIN_3V3 is unavailable, this is an indicator that there is a dead-battery or no-battery condition.

8.3.5.1 Power-On and Supervisory Functions

A power-on-reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a good supply is present. In addition to the POR and supervisory circuits for the internal supplies, a separate programmable voltage supervisor monitors the VOUT_3V3 voltage.

8.3.5.2 Supply Switch-Over

VIN_3V3 takes precedence over VBUS, meaning that when both supply voltages are present the TPS65986 will power from VIN_3V3. Refer to The Figure 46 for a diagram showing the power supply path block. There are two cases in with a power supply switch-over will occur. The first is when VBUS is present first and then VIN_3V3 becomes available. In this case, the supply will automatically switch-over to VIN_3V3 and brown-out prevention is verified by design. The other way a supply switch-over will occur is when both supplies are present and VIN_3V3 is removed and falls below 2.85 V. In this case, a hard reset of the TPS65986 occurs prompting a re-boot.

8.3.5.3 RESETZ and MRESET

The VIN_3V3 voltage is connected to the VOUT_3V3 output by a single FET switch (S2 in Figure 46).

The enabling of the switch is controlled by the core digital circuitry and the conditions are programmable. A supervisor circuit monitors the voltage at VOUT_3V3 for an undervoltage condition and sets the external indicator RESETZ. The RESETZ pin is active low (low when an undervoltage condition occurs). The RESETZ output is also asserted when the MRESET input is asserted. The MRESET input is active-high by default, but is configurable to be active low. Figure 4 shows the RESETZ timing with MRESET set to active high. When VOUT_3V3 is disabled, a resistance of RPDOUT_3V3 pulls down on the pin.

8.3.6 Digital Core

Figure 47 shows a simplified block diagram of the digital core. This diagram shows the interface between the digital and analog portions of the TPS65986.

TPS65986 fig_65986_8p2_FBD_digital_core_source.gif Figure 47. Digital Core Block Diagram

8.3.7 USB-PD BMC Modem Interface

The USB-PD BMC modem interface is a fully USB-PD compliant Type-C interface. The modem contains the BMC encoder/decoder, the TX/Rx FIFOs, the packet engine for construction/deconstruction of the USB-PD packet. This module contains programmable SOP values and processes all SOP headers.

8.3.8 System Glue Logic

The system glue logic module performs various system interface functions such as control of the system interface for RESETZ, MRESET, and VOUT_3V3. This module supports various hardware timers for digital control of analog circuits.

8.3.9 Power Reset Congrol Module (PRCM)

The PRCM implements all clock management, reset control, and sleep mode control.

8.3.10 Interrupt Monitor

The Interrupt Control module handles all interrupt from the external GPIO as well as interrupts from internal analog circuits.

8.3.11 ADC Sense

The ADC Sense module is a digital interface to the SAR ADC. The ADC converts various voltages and currents from the analog circuits. The ADC converts up to 11 channels from analog levels to digital signals. The ADC can be programmed to convert a single sampled value.

8.3.12 UART

Digital UARTS are provided for serial communication. The UART_RX/TX pins are typically used to daisy chain two TPS65986 devices in series to share application code at startup.

8.3.13 I2C Slave

An I2C interface provides interface to the digital core from the system. This interfaces is an I2C slave and supports low-speed and full-speed signaling. See the I2C Slave Interface section for more information.

8.3.14 SPI Master

The SPI master provides a serial interface to an external flash memory. The recommended memory is the W25Q80DV 8 Mbit Serial Flash Memory. A memory of at least 2 Mbit is required when the TPS65986 is using the memory in an unshared manner. A memory of at least 8 Mbit is required when the TPS65986 is using the memory in an shared manner. See the SPI Master Interface section for more information.

8.3.15 Single-Wire Debugger Interface

The SWD interface provides a mechanism to directly master the digital core.

8.3.16 DisplayPort HPD Timers

To enable DisplayPort HPD signaling through PD messaging, two GPIO pins (GPIO4, GPIO5) are used as the HPD input and output. When events occur on this pins during a DisplayPort connection through the Type-C connector (configured in firmware), hardware timers trigger and interrupt the digital core to indicated needed PD messaging. Table 5 shows each I/O function when GPIO4/5 are configured in HPD mode. When HPD is not enabled via firmware, both GPIO4 and GPIO5 remain generic GPIO and may be programmed for other functions. Figure 48 and Figure 49.

Table 5. HPD GPIO Configuration

HPD (Binary) Configuration GPIO4 GPIO5
00 HPD TX Generic GPIO
01 HPD RX Generic GPIO
10 HPD TX HPD RX
11 HPD TX/RX (bidirectional) Generic GPIO
TPS65986 fig_65982_8p3_Features_HPD_RX.gif Figure 48. HPD RX Flow
TPS65986 fig_65982_8p3_Features_HPD_TX.gif Figure 49. HPD TX Flow Diagram

8.3.17 ADC

The TPS65986 ADC is shown in Figure 50. The ADC is a 10-bit successive approximation ADC. The input to the ADC is an analog input multiplexer that supports multiple inputs from various voltages and currents in the device. The output from the ADC is available to be read and used by application firmware. Each supply voltage into the TPS65986 is available to be converted including the port power path inputs and outputs. All GPIO, the C_CCn pins, the charger detection voltages are also available for conversion. To read the port power path current sourced to VBUS, the high-voltage and low-voltage power paths are sensed and converted to voltages to be read by the ADC.

TPS65986 fig_65986_8p2_FBD_sar_adc_source_v3.gif Figure 50. SAR ADC

8.3.17.1 ADC Divider Ratios

The ADC voltage inputs are each divided down to the full-scale input of 1.2 V. The ADC current sensing elements are not divided.

Table 6 shows the divider ratios for each ADC input. The table also shows which inputs are auto-sequenced in the round robin automatic readout mode. The C_CC1 and C_CC2 pin voltages each have two conversions values. The divide-by-5 (CCn_BY5) conversion is intended for use when the C_CCn pin is configured as VCONN output and the divide-by-2 (CCn_BY2) conversion is intended for use when C_CCn pin is configured as the CC data pin.

Table 6. ADC Divider Ratios

CHANNEL # SIGNAL TYPE AUTO-SEQUENCED DIVIDER RATIO BUFFERED
0 Thermal Sense Temperature Yes N/A No
1 VBUS Voltage Yes 25 No
2 SENSEP Voltage Yes Yes No
3 I_RSENSE Current Yes N/A No
4 PP_HV Voltage Yes 25 No
5 IPP_HV Current Yes N/A No
6 PP_5V0 Voltage Yes 5 No
7 IPP_5V0 Current Yes N/A No
8 CC1_BY5 Voltage Yes 5 Yes
9 IPP_CABLE Current Yes N/A No
10 CC2_BY5 Voltage Yes 5 Yes
11 GPIO5 Voltage No 1 No
12 CC1_BY2 Voltage No 2 Yes
13 CC2_BY2 Voltage No 2 Yes
14 PP_CABLE Voltage No 5 No
15 VIN_3V3 Voltage No 3 No
16 VOUT_3V3 Voltage No 3 No
17 BC_ID Voltage No 3 Yes
18 LDO_1V8A Voltage No 2 No
19 LDO_1V8D Voltage No 2 No
20 LDO_3V3 Voltage No 3 No
21 I2C_ADDR Voltage No 3 Yes
22 GPIO0 Voltage No 3 Yes
23 GPIO1 Voltage No 3 Yes
24 GPIO2 Voltage No 3 Yes
25 GPIO3 Voltage No 3 Yes
26 GPIO4 Voltage No 3 Yes
27 GPIO5 Voltage No 3 Yes
28 GPIO6 Voltage No 3 Yes
29 GPIO7 Voltage No 3 Yes
30 GPIO8 Voltage No 3 Yes
31 BUSPOWERZ Voltage No 3 Yes

8.3.17.2 ADC Operating Modes

The ADC is configured into one of three modes: single channel readout, round robin automatic readout and one time automatic readout.

8.3.17.3 Single Channel Readout

In Single Channel Readout mode, the ADC reads a single channel only. Once the channel is selected by firmware, a conversion takes place followed by an interrupt back to the digital core. Figure 5 shows the timing diagram for a conversion starting with an ADC enable. When the ADC is disabled and then enabled, there is an enable time T_ADC_EN (programmable) before sampling occurs. Sampling of the input signal then occurs for time T_SAMPLE (programmable) and the conversion process takes time T_CONVERT (12 clock cycles). After time T_CONVERT, the output data is available for read and an Interrupt is sent to the digital core for time T_INTA (2 clock cycles).

In Single Channel Readout mode, the ADC can be configured to continuously convert that channel. Figure 6 shows the ADC repeated conversion process. In this case, once the interrupt time has passed after a conversion, a new sample and conversion occurs.

8.3.17.4 Round Robin Automatic Readout

When this mode is enabled, the ADC state machine will read from channel 0 to channel 11 and place the converted data into registers. The host interface can request to read from the registers at any time. During Round Robin Automatic Readout, the channel averaging must be set to 1 sample.

When the TPS65986 is running a Round Robin Readout, it will take approximately 696 μs (11 channels × 63.33 μs conversion) to fully convert all channels. Since the conversion is continuous, when a channel is converted, it will overwrite the previous result. Therefore, when all channels are read, any given value may be 649 μs out of sync with any other value.

8.3.17.5 One Time Automatic Readout

The One Time Automatic Readout mode is identical to the Round Robin Automatic Readout except the conversion process halts after the final channel is converted. Once all 11 channels are converted, an interrupt occurs to the digital core.

8.3.18 I/O Buffers

Table 7 lists the I/O buffer types and descriptions. Table 8 lists the pin to I/O buffer mapping for cross-referencing a pin’s particular I/O structure. The following sections show a simplified version of the architecture of each I/O buffer type.

Table 7. I/O Buffer Type Description

BUFFER TYPE DESCRIPTION
IOBUF_GPIOHSSWD General Purpose High-Speed I/O
IOBUF_GPIOHSSPI General Purpose High-Speed I/O
IOBUF_GPIOLS General Purpose Low-Speed I/O
IOBUF_GPIOLSI2C General Purpose Low-Speed I/O with I2C de-glitch time
IOBUF_I2C I2C Compliant Clock/Data Buffers
IOBUF_OD Open-Drain Output
IOBUF_UTX Push-Pull output buffer for UART
IOBUF_URX Input buffer for UART
IOBUF_PORT Input buffer between 1st/2nd stage Port Data Multiplexer

Table 8. Pin to I/O Buffer Mapping

I/O GROUP/PIN BUFFER TYPE SUPPLY CONNECTION (DEFAULT FIRST)
DEBUG1/2/3/4 IOBUF_GPIOLS LDO_3V3, VDDIO
DEBUG_CTL1/2 IOBUF_GPIOLSI2C LDO_3V3, VDDIO
BUSPOWERZ IOBUF_GPIOLS LDO_3V3, VDDIO
GPIO0-8 IOBUF_GPIOLS LDO_3V3, VDDIO
I2C_IRQZ IOBUF_OD LDO_3V3, VDDIO
I2C_SDA/SCL IOBUF_I2C LDO_3V3, VDDIO
MRESET IOBUF_GPIOLS LDO_3V3, VDDIO
RESETZ IOBUF_GPIOLS LDO_3V3, VDDIO
UART_RX IOBUF_URX LDO_3V3, VDDIO
UART_TX IOBUF_UTX LDO_3V3, VDDIO
PORT_INT IOBUF_PORT LDO_3V3
SPI_MOSI/MISO/CLK/SSZ IOBUF_GPIOHSSPI LDO_3V3
SWD_CLK/DATA IOBUF_GPIOHSSWD LDO_3V3

8.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C

Figure 51 shows the GPIO I/O buffer for all GPIOn pins listed GPIO0-GPIO17 in . GPIOn pins can be mapped to USB Type-C, USB PD, and application-specific events to control other ICs, interrupt a host processor, or receive input from another IC. This buffer is configurable to be a push-pull output, a weak push-pull, or open drain output. When configured as an input, the signal can be a de-glitched digital input or an analog input to the ADC. The push-pull output is a simple CMOS output with independent pull-down control allowing open-drain connections. The weak push-pull is also a CMOS output, but with GPIO_RPU resistance in series with the drain. The supply voltage to this buffer is configurable to be LDO_3V3 by default or VDDIO. For simplicity, the connection to VDDIO is not shown in Figure 51, but the connection to VDDIO is fail-safe and a diode will not be present from GPIOn to VDDIO in this configuration. The pull-up and pull-down output drivers are independently controlled from the input and are enabled or disabled via application code in the digital core.

TPS65986 fig_65982_8p2_FBD_io_buffer_gpio_20ns.gif Figure 51. IOBUF_GPIOLS (General GPIO) I/O

Figure 52 shows the IOBUF_GPIOLSI2C that is identical to IOBUF_GPIOLS with an extended de-glitch time.

TPS65986 fig_65982_8p2_FBD_io_buffer_gpio_50ns.gif Figure 52. IOBUF_GPIOLSI2C (General GPIO) I/O with I2C De-glitch

8.3.18.2 IOBUF_OD

The open-drain output driver is shown in Figure 53 and is the same push-pull CMOS output driver as the GPIO buffer. The output has independent pull-down control allowing open-drain connections.

TPS65986 fig_65982_8p2_FBD_io_buffer_od.gif Figure 53. IOBUF_OD Output Buffer

8.3.18.3 IOBUF_UTX

The push-pull output driver is shown in Figure 54. The output buffer has a UARTTX_RO source resistance. The supply voltage to the system side buffer is configurable to be LDO_3V3 by default or VDDIO. This is not shown in Figure 54. The supply voltage to the port side buffers remains LDO_3V3.

TPS65986 fig_65982_8p2_FBD_io_buffer_uarttx.gif Figure 54. IOBUF_UTX Output Buffer

8.3.18.4 IOBUF_URX

The input buffer is shown in Figure 55. The supply voltage to the system side buffer is configurable to be LDO_3V3 by default or VDDIO. This is not shown in Figure 55. The supply voltage to the port side buffers remains LDO_3V3.

TPS65986 fig_65982_8p2_FBD_io_buffer_uartrx.gif Figure 55. IOBUF_URX Input

8.3.18.5 IOBUF_PORT

The input buffer is shown in Figure 56. This input buffer is connected to the intermediate nodes between the 1st stage switch and the 2nd stage switch for each port output (C_USB_TP/N, C_USB_BN/P). The input buffer is enabled via firmware when monitoring digital signals and disabled when an analog signal is desired. See the Signal Monitoring and Pull-up/Pull-down section for more detail on the pull-up and pull-down resistors of the intermediate node.

TPS65986 fig_65982_8p2_FBD_io_buffer_rfu.gif Figure 56. IOBUF_PORT Input Buffer

8.3.18.6 IOBUF_I2C

The I2C I/O driver is shown in Figure 57. This I/O consists of an open-drain output and an input comparator with de-glitching. The supply voltage to this buffer is configurable to be LDO_3V3 by default or VDDIO. This is not shown in Figure 57. Parameters for the I2C clock and data I/Os are found in I2C Slave Requirements and Characteristics.

TPS65986 fig_65982_8p2_FBD_io_buffer_i2c.gif Figure 57. IOBUF_I2C I/O

8.3.18.7 IOBUF_GPIOHSPI

Figure 58 shows the I/O buffers for the SPI interface.

TPS65986 fig_65982_8p2_FBD_io_buffer_spi.gif Figure 58. IOBUF_GPIOHSSPI

8.3.18.8 IOBUF_GPIOHSSWD

Figure 59 shows the I/O buffers for the SWD interface. The CLK input path is a comparator with a pull-up resistor, SWD_RPU, on the pin. The data I/O consists of an identical input structure as the CLK input but with a tri-state CMOS output driver.

TPS65986 fig_65982_8p2_FBD_io_buffer_swd.gif Figure 59. IOBUF_GPIOHSSWD

8.3.19 Thermal Shutdown

The TPS65986 has both a central thermal shutdown to the chip and a local thermal shutdown for the power path block. The central thermal shutdown monitors the temperature of the center of the die and disables all functions except for supervisory circuitry and halts digital core when die temperature goes above a rising temperature of TSD_MAIN. The temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this value, the device resumes normal operation. The power path block has its own local thermal shutdown circuit to detect an over temperature condition due to over current and quickly turn off the power switches. The power path thermal shutdown values are TSD_PWR and TSDH_PWR. The output of the thermal shutdown circuit is de-glitched by TSD_DG before triggering. The thermal shutdown circuits interrupt to the digital core.

8.3.20 Oscillators

The TPS65986 has two independent oscillators for generating internal clock domains. A 48-MHz oscillator generates clocks for the core during normal operation and clocks for the USB 2.0 endpoint physical layer. An external resistance is placed on the R_OSC pin to set the oscillator accuracy. A 100-kHz oscillator generates clocks for various timers and clocking the core during low-power states.

8.4 Device Functional Modes

8.4.1 Boot Code

The TPS65986 has a Power-on-Reset (POR) circuit that monitors LDO_3V3 and issues an internal reset signal. The digital core, memory banks, and peripherals receive clock and RESET interrupt is issued to the digital core and the boot code starts executing. Figure 60 provides the TPS65986 boot code sequence.

The TPS65986 boot code is loaded from OTP on POR, and begins initializing TPS65986 settings. This initialization includes enabling and resetting internal registers, loading trim values, waiting for the trim values to settle, and configuring the device I2C addresses.

The unique I2C address is based on fixed values in OTP and the resistor configuration on the I2C_ADDR pin.

Once initial device configuration is complete the boot code determines if the TPS65986 is booting under dead battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65986 is booting under dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS power to the system.

TPS65986 fig_65982_8p4_DFM_Basic_Boot_Flow.gif Figure 60. Flow Diagram for Boot Code Sequence

8.4.2 Initialization

During initialization the TPS65986 enables device internal hardware and loads default configurations. The 48-MHz clock is enabled and the TPS65986 persistence counters begin monitoring VBUS and VIN_3V3. These counters ensure the supply powering the TPS65986 is stable before continuing the initialization process. The initialization concludes by enabling the thermal monitoring blocks and thermal shutdown protection, along with the ADC, CRC, GPIO and NVIC blocks.

8.4.3 I2C Configuration

The TPS65986 features an I2C bus with a configurable slave address. The I2C address is determined according to the flow depicted in Figure 61. The address is configured by reading device GPIO states at boot (refer to the I2C Pin Address Setting section for details). Once the I2C address is established the TPS65986 enables a limited host interface to allow for communication with the device during the boot process.

TPS65986 fig_65986_8p4_DFM_I2C_Address_Config_source.gif Figure 61. I2C Address Configuration

8.4.4 Dead-Battery Condition

After I2C configuration concludes the TPS65986 checks VIN_3V3 to determine the cause of device boot. If the device is booting from a source other than VIN_3V3, the dead battery flow is followed to allow for the rest of the system to receive power. The state of the BUSPOWERZ pin is read to determine power path configuration for dead battery operation. After the power path is configured, the TPS65986 will continue through the boot process. Figure 62 depicts the full dead battery process.

TPS65986 fig_65986_8p4_DFM_Dead_Battery_Flow_source.gif Figure 62. Dead-Battery Condition Flow Diagram

8.4.5 Application Code

The TPS65986 application code is stored in an external flash memory. The flash memory used for storing the TPS65986 application code may be shared with other devices in the system. The flash memory organization shown in Figure 63 supports the sharing of the flash as well as the TPS65986 using the flash without sharing.

The flash is divided into two separate regions, the Low Region and the High Region. The size of this region is flexible and only depends on the size of the flash memory used. The two regions are used to allow updating the application code in the memory without over-writing the previous code. This ensures that the new updated code is valid before switching to the new code. For example, if a power loss occurred while writing new code, the original code is still in place and used at the next boot.

TPS65986 fig_65982_8p4_DFM_Flash_Memory_Organization.gif Figure 63. Flash Memory Organization

There are two 4 kB header blocks starting at address 0x000000h. The Low Header 4 kB block is at address 0x000000h and the High Header 4 kB block is at 0x001000h. Each header contains a Region Pointer (RPTR) that holds the address of the physical location in memory where the low region application code resides. Each also contains an Application Code Offset (AOFF) that contains the physical offset inside the region where the TPS65986 application code resides. The TPS65986 firmware physical location in memory is RPTR + AOFF. The first sections of the TPS65986 application code contain device configuration settings where CSIZE is a maximum of 4 kB. This configuration determines the devices default behavior after power-up and can be customized using the TPS65986 Configuration Tool. These pointers may be valid or invalid. The Flash Read flow handles reading and determining whether a region is valid and contains good application code.

8.4.6 Flash Memory Read

The TPS65986 first attempts to load application code from the low region of the attached flash memory. If any part of the read process yields invalid data, the TPS65986 will abort the low region read and attempt to read from the high region. If both regions contain invalid data the device carries out the Invalid Memory flow. Figure 64 shows the flash memory read flow.

TPS65986 fig_65982_8p4_DFM_Flash_Read_Flow.gif Figure 64. Flash Read Flow

8.4.7 Invalid Flash Memory

If the flash memory read fails due to invalid data, the TPS65986 carries out the memory invalid flow and presents the SWD interface on the USB Type-C SBU pins.

Memory Invalid Flow depicts the invalid memory process.

TPS65986 fig_65982_8p4_DFM_Invalid_Memory_Flow.gif Figure 65. Memory Invalid Flow

8.4.8 UART Download

The secondary TPS65986 downloads the needed application code from the primary TPS65986 via UART. Figure 66 depicts the UART download process.

Currently the TPS65986 firmware only supports 2 device (1 primary + 1 secondary) systems.

TPS65986 fig_65982_8p4_DFM_UART_Download_Process.gif Figure 66. UART Download Process

8.5 Programming

8.5.1 SPI Master Interface

The TPS65986 loads flash memory during the Boot Code sequence. The SPI master electrical characteristics are defined in SPI Master Characteristics and timing characteristics are defined in Figure 8. The TPS65986 is designed to power the flash from LDO_3V3 in order to support dead-battery or no-battery conditions, and therefore pull-up resistors used for the flash memory must be tied to LDO_3V3. The flash memory IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 1 Mbyte (equivalent to 8 Mbit) to hold the standard application code outlined in Application Code. The SPI master of the TPS65986 supports SPI Mode 0. For Mode 0, data delay is defined such that data is output on the same cycle as chip select (SPI_SSZ pin) becomes active. The chip select polarity is active-low. The clock phase is defined such that data (on the SPI_MISO and SPI_MOSI pins) is shifted out on the falling edge of the clock (SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is defined such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be 4 kB. The W25Q80 flash memory IC is recommended. Refer to TPS65986 I2C Host Interface Specification for instructions for interacting with the attached flash memory over SPI using the host interface of the TPS65986.

8.5.2 I2C Slave Interface

The TPS65986 has one I2C interface port. The I2C Port is comprised of the I2C_SDA, I2C_SCL, and I2C_IRQZ pins. This interfaces provide general status information about the TPS65986, as well as the ability to control the TPS65986 behavior, as well as providing information about connections detected at the USB-C receptacle and supporting communications to/from a connected device and/or cable supporting BMC USB-PD.

The I2C port can be a master or a slave, but the default behavior is to be a slave. An interrupt mask is set for the port to determine what events are interrupted on the port.

8.5.2.1 I2C Interface Description

The TPS65986 supports Standard and Fast mode I2C interface. The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor. Data transfer may be initiated only when the bus is not busy.

A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high.

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 67 shows the start and stop conditions of the transfer. Figure 68 shows the SDA and SCL signals for transferring a bit. Figure 69 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

TPS65986 fig_65982_8p5_Prog_i2c_start_stop.gif Figure 67. I2C Definition of Start and Stop Conditions
TPS65986 fig_65982_8p5_Prog_i2c_bit_transfer.gif Figure 68. I2C Bit Transfer
TPS65986 fig_65982_8p5_Prog_i2c_bit_acknowledge.gif Figure 69. I2C Acknowledgment

8.5.2.2 I2C Clock Stretching

The TPS65986 features clock stretching for the I2C protocol. The TPS65986 slave I2C port may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The master communicating with the slave must not finish the transmission of the current bit and must wait until the clock line actually goes high. When the slave is clock stretching, the clock line will remain low.

The master must wait until it observes the clock line transition to high plus an additional minimum time (4 μs for standard 100 kbps I2C) before pulling the clock low again.

Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.

8.5.2.3 I2C Address Setting

The boot code sets the hardware configurable unique I2C address of the TPS65986 before the port is enabled to respond to I2C transactions. The unique I2C address is determined the analog level set by the resistance on the I2C_ADDR strap pin (three bits) as shown in Table 9.

Table 9. I2C Default Unique Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 1 1 1 I2C_ADDR_DECODE[2:0] R/W

8.5.2.4 Unique Address Interface

The Unique Address Interface allows for complex interaction between an I2C master and a single TPS65986. The I2C Slave sub-address is used to receive or respond to Host Interface protocol commands. Figure 70 and Figure 71 show the write and read protocol for the I2C slave interface, and a key is included in Figure 72 to explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated here in part.

TPS65986 fig_65982_8p5_Prog_i2c_write_command_protocol.gif Figure 70. I2C Unique Address Write Register Protocol
TPS65986 fig_65982_8p5_Prog_i2c_read_command_protocol.gif Figure 71. I2C Unique Address Read Register Protocol
TPS65986 fig_65982_8p5_Prog_i2c_bit_legend.gif Figure 72. I2C Read/Write Protocol Key

8.5.2.5 I2C Pin Address Setting

To enable the setting of multiple I2C addresses using a single TPS65986 pin, a resistance is placed externally on the I2C_ADDR pin. The internal ADC then decodes the address from this resistance value. Figure 73 shows the decoding. DEBUG_CTL1/2 are checked at the same time for the DC condition on this pin (high or low) for setting other bits of the address described previously. Note, DEBUG_CTL1/2 are GPIO and the address decoding is done by firmware in the digital core.

TPS65986 fig_65986_8p5_Prog_i2c_address_decode.gif Figure 73. I2C Address Decode

Table 10 lists the external resistance needed to set bits [3:1] of the I2C Unique Address. For the Primary TPS65986 (UART Master), the I2C_ADDR pin is grounded and this TPS65986 device is connected to the SPI Flash. In a two Type-C port system sharing one SPI Flash, I2C_ADDR is left as an open-circuit (UART Slave 1) and this TPS65986 is referred to as the Secondary. Other I2C_ADDR terminations may be used to resolve I2C address conflicts when multiple I2C slaves share the same bus.

Table 10. I2C Address Resistance

The TPS65986
DEVICE
EXTERNAL
RESISTANCE (1%)
I2C UNIQUE
ADDRESS [3:1]
SPI Owner, UART Master 0 (Primary) 0 Ω 0x00
UART Slave 7 38.3 kΩ 0x01
UART Slave 6 84.5 kΩ 0x02
UART Slave 5 140 kΩ 0x03
UART Slave 4 205 kΩ 0x04
UART Slave 3 280 kΩ 0x05
UART Slave 2 374 kΩ 0x06
UART Slave 1 (Secondary) Open 0x07