SLVSD13C October 2015 – August 2016 TPS65986
Refer to the PDF data sheet for device specific package drawings
Proper routing and placement will maintain signal integrity for high-speed signals and improve the thermal dissipation from the TPS65986 power path. The combination of power and high-speed data signals are easily routed if the following guidelines are followed. It is a best practice to consult with a printed circuit board (PCB) manufacturer to verify manufacturing capabilities.
Figure 88 shows the TPS65986 footprint using a 0.25mm pad diameter. This footprint is applicable to boards that will be using an HDI PCB process that uses smaller vias to fan-out into the inner layers of the PCB. This footprint requires via fill and tenting and is recommended for size-constrained applications. The circular footprint allows for easy fan-out into other layers of the PCB and better thermal dissipation into the GND planes. Figure 89 shows the recommended via sizing for use under the balls. The size is 5mil hole and 10mil diameter. This via size will allow for approximately 1.5A current rating at 3 mΩ of DC resistance with 1.6nH of inductance. It is recommended to verify these numbers with board manufacturing processes used in fabrication of the PCB. This footprint is available for download on the TPS65986 product folder on the TPS65986 product folder.
Figure 90 shows the TPS65986 footprint using oval-shaped pads in specific locations. This allows the PCB designer to route the inner perimeter balls through the top layer. The balls around the perimeter have their pads in an oval shape with the exception of the corner balls. Figure 91 shows the sizing for the oval pads, 0.25 mm by 0.17 mm. All of the other non-oval shaped pads will have a 0.25 mm diameter. This footprint is recommended for MDI (Medium Density) PCB designs that are generally less expensive to build. The void under the TPS65986 allows for vias to route the inner signals and connect to the GND and power planes. Figure 92 shows the recommended minimum via size (8mil hole and 16 mil diameter). The recommended 8mil vias will be rated for approximately 1.8 A of DC current and 1.5 mΩ of resistance with 1.3 nH of inductance. Some board manufactures may offer 6mil hole and 12 mil diameter vias with a mechanical drill. This footprint is available for download on the TPS65986 product folder.
When the TPS65986 is placed on top and its components on bottom the solution size will be at its smallest. The solution size will average less than 64 mm2 (8 mm × 8 mm). Selection of the oval pad TPS65986 footprint or standard TPS65986 footprint will allow for similar results.
The oval pad footprint layout is generally more difficult to route than the standard footprint due to the top layer fan-out and void via placement needed; however, when the footprint with oval pads is used, “Via on Pads,” laser-drilled vias, and HDI board processes are not required. Therefore, a footprint with oval pads is ideal for cost-optimized applications and will be used for the following the layout example. This layout example follows the charger application example (see Typical Application) and includes all necessary passive components needed for this application. This design uses the internal high voltage FET path for sourcing and sinking power respectively. All I/O will be fanned out to provide an example for routing out all pins, not all designs will utilize all of the I/O on the TPS65986.
Placement of components on the top and bottom layers is used for this example to minimize solution size. The TPS65986 is placed on the top layer of the board and the majority of its components are placed on the bottom layer. When placing the components on the bottom layer, it is recommended that they are placed directly under the TPS65986 in a manner where the pads of the components are not directly under the void on the top layer. Figure 93 and Figure 94 show the placement in 2-D. Figure 95 and Figure 96 show the placement in 3-D.
When starting to route nets it is best to start with 4 mil clearance spacing. The designer may have to adjust the 4mil clearance to 3.5 mil when fanning out the top layer routes. With the routing of the top layer having a tight clearance, it is recommended to have the layout grid snapped to 1 mil. For certain routes on the layout done in this guide, the grid snap was set to 0.1 mil. For component spacing this design used 20 mil clearance between components. The silk screen around certain passive components may be deleted to allow for closer placement of components.
On the top layer, create pours for PP_HV, PP_5V0 and VBUS to extend area to place 8 mil hole and 16 mil diameter vias to connect to the bottom layer. A minimum of 4 vias is needed to connect between the top and bottom layer. For the bottom layer, place pours that will connect the PP_HV, PP_5V0, and VBUS capacitors to their respective vias.
The next step is to route the connections to the passive components on the top and bottom layers. For the top layer only CC1 and CC2 capacitors will be placed on top. Routing the CC1 and CC2 lines with a 8 mil trace will facilitate the needed current for supporting powered Type C cables through VCONN. For more information on VCONN please refer to the Type C specification. Figure 99 shows how to route to the CC1 and CC2 to their respective capacitors. For capacitor GND pin use a 10 mil trace if possible. This particular system support Dead Battery, which has RPD_G1/2 connected to CC1/2.
The top layer pads will have to be connected the bottom placed component through Vias (8 mil hole and 16 mil diameter recommended). For the VIN_3V3, VDDIO, LDO_3V3, LDO_1V8A, LDO1V8D, LDO_BMC, and VOUT_3V3 use 6 mil traces to route. For PP_CABLE route using an 8 mil trace and for all other routes 4 mil traces may be used. To allow for additional space for routing, stagger the component vias to leave room for routing other signal nets. Figure 100 and Figure 101 show the top and bottom routing. Table 17 provides a summary of the trace widths.
|CC1, CC2, PP_CABLE||8|
|LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VIN_3V3, VOUT_3V3, VDDIO\||6|
The void under the TPS65986 is used to via out I/O and for thermal relief vias. A minimum of 6 vias must be used for thermal dissipation to the GND planes. The thermal relief vias must be placed on the right side of the device by the power path. Figure 102 shows the recommended placement of the vias. Figure 103 shows the top layer GND pour to connect the vias and GND balls together.
Once the components are routed, the rest of the area can be used to route all of the additional I/O. After all nets have been routed place a polygonal pour under to connect the TPS65986 GND pins to the GND vias. Refer to Figure 104 for the final top routing and GND pour.
The inner signal layer is used to route the I/O from the internal balls of the TPS65986. Figure 105 shows how to route the internal layer.
The bottom layer has most of the components placed and routed already. Place a polygon pour to connect all of the GND nets and vias on the bottom layer, refer to Figure 106.