SLVSD13C October   2015  – August 2016 TPS65986


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Power Consumption Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 6.11 Port Power Switch Characteristics
    12. 6.12 Port Data Multiplexer Switching and Timing Characteristics
    13. 6.13 Port Data Multiplexer Clamp Characteristics
    14. 6.14 Port Data Multiplexer SBU Detection Requirements
    15. 6.15 Port Data Multiplexer Signal Monitoring Pull-up and Pull-down Characteristics
    16. 6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 6.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 6.19 Input/Output (I/O) Requirements and Characteristics
    20. 6.20 I2C Slave Requirements and Characteristics
    21. 6.21 SPI Master Characteristics
    22. 6.22 Single-Wire Debugger (SWD) Timing Requirements
    23. 6.23 BUSPOWERZ Configuration Requirements
    24. 6.24 HPD Timing Requirements and Characteristics
    25. 6.25 Thermal Shutdown Characteristics
    26. 6.26 Oscillator Requirements and Characteristics
    27. 6.27 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. USB-PD Encoding and Signaling
        2. USB-PD Bi-Phase Marked Coding
        3. USB-PD Transmit (TX) and Receive (Rx) Masks
        4. USB-PD BMC Transmitter
        5. USB-PD BMC Receiver
      2. 8.3.2  Cable Plug and Orientation Detection
        1. Configured as a DFP
        2. Configured as a UFP
        3. Dead-Battery or No-Battery Support
      3. 8.3.3  Port Power Switches
        1.  5V Power Delivery
        2.  5V Power Switch as a Source
        3.  PP_5V0 Current Sense
        4.  PP_5V0 Current Limit
        5.  Internal HV Power Delivery
        6.  Internal HV Power Switch as a Source
        7.  Internal HV Power Switch as a Sink
        8.  Internal HV Power Switch Current Sense
        9.  Internal HV Power Switch Current Limit
        10. Soft Start
        11. BUSPOWERZ
        12. Voltage Transitions on VBUS through Port Power Switches
        13. HV Transition to PP_RV0 Pull-down on VBUS
        14. VBUS Transition to VSAFE0V
        15. C_CC1 and C_CC2 Power Configuration and Power Delivery
        16. PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        17. PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 8.3.4  USB Type-C Port Data Multiplexer
        1.  USB Top and Bottom Ports
        2.  Multiplexer Connection Orientation
        3.  Digital Crossbar Multiplexer
        4.  SBU Crossbar Multiplexer
        5.  Signal Monitoring and Pull-up/Pull-down
        6.  Port Multiplexer Clamp
        7.  USB2.0 Low-Speed Endpoint
        8.  Battery Charger (BC1.2) Detection Block
        9.  BC1.2 Data Contact Detect
        10. BC1.2 Primary and Secondary Detection
      5. 8.3.5  Power Management
        1. Power-On and Supervisory Functions
        2. Supply Switch-Over
        3. RESETZ and MRESET
      6. 8.3.6  Digital Core
      7. 8.3.7  USB-PD BMC Modem Interface
      8. 8.3.8  System Glue Logic
      9. 8.3.9  Power Reset Congrol Module (PRCM)
      10. 8.3.10 Interrupt Monitor
      11. 8.3.11 ADC Sense
      12. 8.3.12 UART
      13. 8.3.13 I2C Slave
      14. 8.3.14 SPI Master
      15. 8.3.15 Single-Wire Debugger Interface
      16. 8.3.16 DisplayPort HPD Timers
      17. 8.3.17 ADC
        1. ADC Divider Ratios
        2. ADC Operating Modes
        3. Single Channel Readout
        4. Round Robin Automatic Readout
        5. One Time Automatic Readout
      18. 8.3.18 I/O Buffers
        2. IOBUF_OD
        3. IOBUF_UTX
        4. IOBUF_URX
        5. IOBUF_PORT
        6. IOBUF_I2C
      19. 8.3.19 Thermal Shutdown
      20. 8.3.20 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Dead-Battery Condition
      5. 8.4.5 Application Code
      6. 8.4.6 Flash Memory Read
      7. 8.4.7 Invalid Flash Memory
      8. 8.4.8 UART Download
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. I2C Interface Description
        2. I2C Clock Stretching
        3. I2C Address Setting
        4. Unique Address Interface
        5. I2C Pin Address Setting
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB Type-C and PD Dongle Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. TPS65986 External Flash
          2. I2C, Debug Control (DEBUG_CTL), and SPI Resistors
          3. Oscillator (R_OSC) Resistor
          4. VBUS Capacitor and Ferrite Bead
          5. Soft Start (SS) Capacitor
          6. Port Power Switch (PP_HV and PP_5V0) Capacitors
          7. Cable Connection (CCn) Capacitors and RPD_Gn Connections
          8. LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. Application Curves
      2. 9.2.2 USB Type-C and PD Dock Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. TPS65986 Primary and Secondary Interaction
        3. Application Curves
      3. 9.2.3 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. Design Requirements
        2. Detailed Design Procedure
          1. TPS65986 and System Controller Interaction
          2. HD3SS460 Control and DisplayPort Configuration
          3. DC Barrel Jack and Type-C PD Charging
          4. Primary TPS65986 Flash Master and Secondary Port
          5. TPS65986 Dead Battery Support Primary and Secondary Port
          6. Debugging Methods
        3. Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 VBUS 3.3-V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
      2. 10.3.2 Schottky for Current Surge Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  TPS65986 Recommended Footprints
        1. Standard TPS65986 Footprint (Circular Pads)
      2. 11.1.2  Alternate TPS65986 Footprint (Oval Pads)
      3. 11.1.3  Top TPS65986 Placement and Bottom Component Placement and Layout
      4. 11.1.4  Oval Pad Footprint Layout and Placement
      5. 11.1.5  Component Placement
      6. 11.1.6  Designs Rules and Guidance
      7. 11.1.7  Routing PP_HV, PP_5V0, and VBUS
      8. 11.1.8  Routing Top and Bottom Passive Components
      9. 11.1.9  Void Via Placement
      10. 11.1.10 Top Layer Routing
      11. 11.1.11 Inner Signal Layer Routing
      12. 11.1.12 Bottom Layer Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Development Support
      2. 12.1.2 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

11 Layout

11.1 Layout Guidelines

Proper routing and placement will maintain signal integrity for high-speed signals and improve the thermal dissipation from the TPS65986 power path. The combination of power and high-speed data signals are easily routed if the following guidelines are followed. It is a best practice to consult with a printed circuit board (PCB) manufacturer to verify manufacturing capabilities.

11.1.1 TPS65986 Recommended Footprints Standard TPS65986 Footprint (Circular Pads)

Figure 88 shows the TPS65986 footprint using a 0.25mm pad diameter. This footprint is applicable to boards that will be using an HDI PCB process that uses smaller vias to fan-out into the inner layers of the PCB. This footprint requires via fill and tenting and is recommended for size-constrained applications. The circular footprint allows for easy fan-out into other layers of the PCB and better thermal dissipation into the GND planes. Figure 89 shows the recommended via sizing for use under the balls. The size is 5mil hole and 10mil diameter. This via size will allow for approximately 1.5A current rating at 3 mΩ of DC resistance with 1.6nH of inductance. It is recommended to verify these numbers with board manufacturing processes used in fabrication of the PCB. This footprint is available for download on the TPS65986 product folder on the TPS65986 product folder.

TPS65986 fig_65982_11_Layout_Footprint_Circular.png Figure 88. Top View Standard TPS65986 Footprint (Circular Pads)
TPS65986 fig_65982_11_Layout_Underball_Vias.png Figure 89. Under Ball Recommended Via Size

11.1.2 Alternate TPS65986 Footprint (Oval Pads)

Figure 90 shows the TPS65986 footprint using oval-shaped pads in specific locations. This allows the PCB designer to route the inner perimeter balls through the top layer. The balls around the perimeter have their pads in an oval shape with the exception of the corner balls. Figure 91 shows the sizing for the oval pads, 0.25 mm by 0.17 mm. All of the other non-oval shaped pads will have a 0.25 mm diameter. This footprint is recommended for MDI (Medium Density) PCB designs that are generally less expensive to build. The void under the TPS65986 allows for vias to route the inner signals and connect to the GND and power planes. Figure 92 shows the recommended minimum via size (8mil hole and 16 mil diameter). The recommended 8mil vias will be rated for approximately 1.8 A of DC current and 1.5 mΩ of resistance with 1.3 nH of inductance. Some board manufactures may offer 6mil hole and 12 mil diameter vias with a mechanical drill. This footprint is available for download on the TPS65986 product folder.

TPS65986 fig_65982_11_Layout_Footprint_Ovular.png Figure 90. Top View Alternate TPS65986 Footprint (Oval Pads)
TPS65986 fig_65982_11_Layout_Ovular_Pad_Sizing.png Figure 91. Oval Pad Sizing
TPS65986 fig_65982_11_Layout_Underball_Via_Sizing.png Figure 92. Recommended Minimum Via Sizing

11.1.3 Top TPS65986 Placement and Bottom Component Placement and Layout

When the TPS65986 is placed on top and its components on bottom the solution size will be at its smallest. The solution size will average less than 64 mm2 (8 mm × 8 mm). Selection of the oval pad TPS65986 footprint or standard TPS65986 footprint will allow for similar results.

11.1.4 Oval Pad Footprint Layout and Placement

The oval pad footprint layout is generally more difficult to route than the standard footprint due to the top layer fan-out and void via placement needed; however, when the footprint with oval pads is used, “Via on Pads,” laser-drilled vias, and HDI board processes are not required. Therefore, a footprint with oval pads is ideal for cost-optimized applications and will be used for the following the layout example. This layout example follows the charger application example (see Typical Application) and includes all necessary passive components needed for this application. This design uses the internal high voltage FET path for sourcing and sinking power respectively. All I/O will be fanned out to provide an example for routing out all pins, not all designs will utilize all of the I/O on the TPS65986.

11.1.5 Component Placement

Placement of components on the top and bottom layers is used for this example to minimize solution size. The TPS65986 is placed on the top layer of the board and the majority of its components are placed on the bottom layer. When placing the components on the bottom layer, it is recommended that they are placed directly under the TPS65986 in a manner where the pads of the components are not directly under the void on the top layer. Figure 93 and Figure 94 show the placement in 2-D. Figure 95 and Figure 96 show the placement in 3-D.

11.1.6 Designs Rules and Guidance

When starting to route nets it is best to start with 4 mil clearance spacing. The designer may have to adjust the 4mil clearance to 3.5 mil when fanning out the top layer routes. With the routing of the top layer having a tight clearance, it is recommended to have the layout grid snapped to 1 mil. For certain routes on the layout done in this guide, the grid snap was set to 0.1 mil. For component spacing this design used 20 mil clearance between components. The silk screen around certain passive components may be deleted to allow for closer placement of components.

11.1.7 Routing PP_HV, PP_5V0, and VBUS

On the top layer, create pours for PP_HV, PP_5V0 and VBUS to extend area to place 8 mil hole and 16 mil diameter vias to connect to the bottom layer. A minimum of 4 vias is needed to connect between the top and bottom layer. For the bottom layer, place pours that will connect the PP_HV, PP_5V0, and VBUS capacitors to their respective vias.

11.1.8 Routing Top and Bottom Passive Components

The next step is to route the connections to the passive components on the top and bottom layers. For the top layer only CC1 and CC2 capacitors will be placed on top. Routing the CC1 and CC2 lines with a 8 mil trace will facilitate the needed current for supporting powered Type C cables through VCONN. For more information on VCONN please refer to the Type C specification. Figure 99 shows how to route to the CC1 and CC2 to their respective capacitors. For capacitor GND pin use a 10 mil trace if possible. This particular system support Dead Battery, which has RPD_G1/2 connected to CC1/2.

The top layer pads will have to be connected the bottom placed component through Vias (8 mil hole and 16 mil diameter recommended). For the VIN_3V3, VDDIO, LDO_3V3, LDO_1V8A, LDO1V8D, LDO_BMC, and VOUT_3V3 use 6 mil traces to route. For PP_CABLE route using an 8 mil trace and for all other routes 4 mil traces may be used. To allow for additional space for routing, stagger the component vias to leave room for routing other signal nets. Figure 100 and Figure 101 show the top and bottom routing. Table 17 provides a summary of the trace widths.

Table 17. Routing Trace Widths

Component GND 10

11.1.9 Void Via Placement

The void under the TPS65986 is used to via out I/O and for thermal relief vias. A minimum of 6 vias must be used for thermal dissipation to the GND planes. The thermal relief vias must be placed on the right side of the device by the power path. Figure 102 shows the recommended placement of the vias. Figure 103 shows the top layer GND pour to connect the vias and GND balls together.

11.1.10 Top Layer Routing

Once the components are routed, the rest of the area can be used to route all of the additional I/O. After all nets have been routed place a polygonal pour under to connect the TPS65986 GND pins to the GND vias. Refer to Figure 104 for the final top routing and GND pour.

11.1.11 Inner Signal Layer Routing

The inner signal layer is used to route the I/O from the internal balls of the TPS65986. Figure 105 shows how to route the internal layer.

11.1.12 Bottom Layer Routing

The bottom layer has most of the components placed and routed already. Place a polygon pour to connect all of the GND nets and vias on the bottom layer, refer to Figure 106.

11.2 Layout Example

TPS65986 fig_65982_11_Layout_Top_View_2D.png Figure 93. Example Layout (Top View in 2-D)
TPS65986 fig_65982_11_Layout_Bottom_View_2D.png Figure 94. Example Layout (Bottom View in 2-D)
TPS65986 fig_65982_11_Layout_Top_View_3D.png Figure 95. Example Layout (Top View in 3-D)
TPS65986 fig_65982_11_Layout_Bottom_View_3D.png Figure 96. Example Layout (Bottom View in 3-D)
TPS65986 fig_65982_11_Layout_Top_Polygonal_Pours.png Figure 97. Top Polygonal Pours
TPS65986 fig_65982_11_Layout_Bottom_Polygonal_Pours.png Figure 98. Bottom Polygonal Pours
TPS65986 fig_65982_11_Layout_CC1_and_CC2_Cap_Routing.png Figure 99. CC1 and CC2 Capacitor Routing
TPS65986 fig_65982_11_Layout_Top_Component_Routing.png Figure 100. Top Layer Component Routing
TPS65986 fig_65982_11_Layout_Bottom_Component_Routing.png Figure 101. Bottom Layer Component Routing
TPS65986 fig_65982_11_Layout_Void_Via_Placement.png Figure 102. Void Via Placement
TPS65986 fig_65982_11_Layout_Top_Layer_GND_Pour.png Figure 103. Top Layer GND Pour
TPS65986 fig_65982_11_Layout_Top_Layer_Final.png Figure 104. Final Routing and GND Pour (Top Layer)
TPS65986 fig_65982_11_Layout_Inner_Layer_Final.png Figure 105. Final Routing (Inner Signal Layer)
TPS65986 fig_65982_11_Layout_Bottom_Layer_Final.png Figure 106. Final Routing (Bottom Layer)