SLVSD13C October   2015  – August 2016 TPS65986

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Power Consumption Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 6.11 Port Power Switch Characteristics
    12. 6.12 Port Data Multiplexer Switching and Timing Characteristics
    13. 6.13 Port Data Multiplexer Clamp Characteristics
    14. 6.14 Port Data Multiplexer SBU Detection Requirements
    15. 6.15 Port Data Multiplexer Signal Monitoring Pull-up and Pull-down Characteristics
    16. 6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 6.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 6.19 Input/Output (I/O) Requirements and Characteristics
    20. 6.20 I2C Slave Requirements and Characteristics
    21. 6.21 SPI Master Characteristics
    22. 6.22 Single-Wire Debugger (SWD) Timing Requirements
    23. 6.23 BUSPOWERZ Configuration Requirements
    24. 6.24 HPD Timing Requirements and Characteristics
    25. 6.25 Thermal Shutdown Characteristics
    26. 6.26 Oscillator Requirements and Characteristics
    27. 6.27 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Cable Plug and Orientation Detection
        1. 8.3.2.1 Configured as a DFP
        2. 8.3.2.2 Configured as a UFP
        3. 8.3.2.3 Dead-Battery or No-Battery Support
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1  5V Power Delivery
        2. 8.3.3.2  5V Power Switch as a Source
        3. 8.3.3.3  PP_5V0 Current Sense
        4. 8.3.3.4  PP_5V0 Current Limit
        5. 8.3.3.5  Internal HV Power Delivery
        6. 8.3.3.6  Internal HV Power Switch as a Source
        7. 8.3.3.7  Internal HV Power Switch as a Sink
        8. 8.3.3.8  Internal HV Power Switch Current Sense
        9. 8.3.3.9  Internal HV Power Switch Current Limit
        10. 8.3.3.10 Soft Start
        11. 8.3.3.11 BUSPOWERZ
        12. 8.3.3.12 Voltage Transitions on VBUS through Port Power Switches
        13. 8.3.3.13 HV Transition to PP_RV0 Pull-down on VBUS
        14. 8.3.3.14 VBUS Transition to VSAFE0V
        15. 8.3.3.15 C_CC1 and C_CC2 Power Configuration and Power Delivery
        16. 8.3.3.16 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        17. 8.3.3.17 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 8.3.4  USB Type-C Port Data Multiplexer
        1. 8.3.4.1  USB Top and Bottom Ports
        2. 8.3.4.2  Multiplexer Connection Orientation
        3. 8.3.4.3  Digital Crossbar Multiplexer
        4. 8.3.4.4  SBU Crossbar Multiplexer
        5. 8.3.4.5  Signal Monitoring and Pull-up/Pull-down
        6. 8.3.4.6  Port Multiplexer Clamp
        7. 8.3.4.7  USB2.0 Low-Speed Endpoint
        8. 8.3.4.8  Battery Charger (BC1.2) Detection Block
        9. 8.3.4.9  BC1.2 Data Contact Detect
        10. 8.3.4.10 BC1.2 Primary and Secondary Detection
      5. 8.3.5  Power Management
        1. 8.3.5.1 Power-On and Supervisory Functions
        2. 8.3.5.2 Supply Switch-Over
        3. 8.3.5.3 RESETZ and MRESET
      6. 8.3.6  Digital Core
      7. 8.3.7  USB-PD BMC Modem Interface
      8. 8.3.8  System Glue Logic
      9. 8.3.9  Power Reset Congrol Module (PRCM)
      10. 8.3.10 Interrupt Monitor
      11. 8.3.11 ADC Sense
      12. 8.3.12 UART
      13. 8.3.13 I2C Slave
      14. 8.3.14 SPI Master
      15. 8.3.15 Single-Wire Debugger Interface
      16. 8.3.16 DisplayPort HPD Timers
      17. 8.3.17 ADC
        1. 8.3.17.1 ADC Divider Ratios
        2. 8.3.17.2 ADC Operating Modes
        3. 8.3.17.3 Single Channel Readout
        4. 8.3.17.4 Round Robin Automatic Readout
        5. 8.3.17.5 One Time Automatic Readout
      18. 8.3.18 I/O Buffers
        1. 8.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 8.3.18.2 IOBUF_OD
        3. 8.3.18.3 IOBUF_UTX
        4. 8.3.18.4 IOBUF_URX
        5. 8.3.18.5 IOBUF_PORT
        6. 8.3.18.6 IOBUF_I2C
        7. 8.3.18.7 IOBUF_GPIOHSPI
        8. 8.3.18.8 IOBUF_GPIOHSSWD
      19. 8.3.19 Thermal Shutdown
      20. 8.3.20 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Dead-Battery Condition
      5. 8.4.5 Application Code
      6. 8.4.6 Flash Memory Read
      7. 8.4.7 Invalid Flash Memory
      8. 8.4.8 UART Download
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. 8.5.2.1 I2C Interface Description
        2. 8.5.2.2 I2C Clock Stretching
        3. 8.5.2.3 I2C Address Setting
        4. 8.5.2.4 Unique Address Interface
        5. 8.5.2.5 I2C Pin Address Setting
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB Type-C and PD Dongle Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 TPS65986 External Flash
          2. 9.2.1.2.2 I2C, Debug Control (DEBUG_CTL), and SPI Resistors
          3. 9.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 9.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 9.2.1.2.5 Soft Start (SS) Capacitor
          6. 9.2.1.2.6 Port Power Switch (PP_HV and PP_5V0) Capacitors
          7. 9.2.1.2.7 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          8. 9.2.1.2.8 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 9.2.1.3 Application Curves
      2. 9.2.2 USB Type-C and PD Dock Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. 9.2.2.2.2 TPS65986 Primary and Secondary Interaction
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 TPS65986 and System Controller Interaction
          2. 9.2.3.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 9.2.3.2.3 DC Barrel Jack and Type-C PD Charging
          4. 9.2.3.2.4 Primary TPS65986 Flash Master and Secondary Port
          5. 9.2.3.2.5 TPS65986 Dead Battery Support Primary and Secondary Port
          6. 9.2.3.2.6 Debugging Methods
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 VBUS 3.3-V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
      2. 10.3.2 Schottky for Current Surge Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  TPS65986 Recommended Footprints
        1. 11.1.1.1 Standard TPS65986 Footprint (Circular Pads)
      2. 11.1.2  Alternate TPS65986 Footprint (Oval Pads)
      3. 11.1.3  Top TPS65986 Placement and Bottom Component Placement and Layout
      4. 11.1.4  Oval Pad Footprint Layout and Placement
      5. 11.1.5  Component Placement
      6. 11.1.6  Designs Rules and Guidance
      7. 11.1.7  Routing PP_HV, PP_5V0, and VBUS
      8. 11.1.8  Routing Top and Bottom Passive Components
      9. 11.1.9  Void Via Placement
      10. 11.1.10 Top Layer Routing
      11. 11.1.11 Inner Signal Layer Routing
      12. 11.1.12 Bottom Layer Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Development Support
      2. 12.1.2 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

7 Parameter Measurement Information

TPS65986 fig_65982_7_Param_Meas_resetz_timing.gif Figure 4. RESETZ Assertion Timing
TPS65986 fig_65982_7_Param_Meas_adc_enable_timing.gif Figure 5. ADC Enable and Conversion Timing
TPS65986 fig_65982_7_Param_Meas_adc_repeat_sample_timing.gif Figure 6. ADC Repeated Conversion Timing
TPS65986 pmi_SCPS253.gif Figure 7. I2C Slave Interface Timing
TPS65986 fig_65982_7_Param_Meas_spi_timing.gif Figure 8. SPI Master Timing
TPS65986 fig_65982_7_Param_Meas_swd_timing.gif Figure 9. SWD Timing