SLVSD13C October   2015  – August 2016 TPS65986

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Power Consumption Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 6.11 Port Power Switch Characteristics
    12. 6.12 Port Data Multiplexer Switching and Timing Characteristics
    13. 6.13 Port Data Multiplexer Clamp Characteristics
    14. 6.14 Port Data Multiplexer SBU Detection Requirements
    15. 6.15 Port Data Multiplexer Signal Monitoring Pull-up and Pull-down Characteristics
    16. 6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 6.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 6.19 Input/Output (I/O) Requirements and Characteristics
    20. 6.20 I2C Slave Requirements and Characteristics
    21. 6.21 SPI Master Characteristics
    22. 6.22 Single-Wire Debugger (SWD) Timing Requirements
    23. 6.23 BUSPOWERZ Configuration Requirements
    24. 6.24 HPD Timing Requirements and Characteristics
    25. 6.25 Thermal Shutdown Characteristics
    26. 6.26 Oscillator Requirements and Characteristics
    27. 6.27 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Cable Plug and Orientation Detection
        1. 8.3.2.1 Configured as a DFP
        2. 8.3.2.2 Configured as a UFP
        3. 8.3.2.3 Dead-Battery or No-Battery Support
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1  5V Power Delivery
        2. 8.3.3.2  5V Power Switch as a Source
        3. 8.3.3.3  PP_5V0 Current Sense
        4. 8.3.3.4  PP_5V0 Current Limit
        5. 8.3.3.5  Internal HV Power Delivery
        6. 8.3.3.6  Internal HV Power Switch as a Source
        7. 8.3.3.7  Internal HV Power Switch as a Sink
        8. 8.3.3.8  Internal HV Power Switch Current Sense
        9. 8.3.3.9  Internal HV Power Switch Current Limit
        10. 8.3.3.10 Soft Start
        11. 8.3.3.11 BUSPOWERZ
        12. 8.3.3.12 Voltage Transitions on VBUS through Port Power Switches
        13. 8.3.3.13 HV Transition to PP_RV0 Pull-down on VBUS
        14. 8.3.3.14 VBUS Transition to VSAFE0V
        15. 8.3.3.15 C_CC1 and C_CC2 Power Configuration and Power Delivery
        16. 8.3.3.16 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        17. 8.3.3.17 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 8.3.4  USB Type-C Port Data Multiplexer
        1. 8.3.4.1  USB Top and Bottom Ports
        2. 8.3.4.2  Multiplexer Connection Orientation
        3. 8.3.4.3  Digital Crossbar Multiplexer
        4. 8.3.4.4  SBU Crossbar Multiplexer
        5. 8.3.4.5  Signal Monitoring and Pull-up/Pull-down
        6. 8.3.4.6  Port Multiplexer Clamp
        7. 8.3.4.7  USB2.0 Low-Speed Endpoint
        8. 8.3.4.8  Battery Charger (BC1.2) Detection Block
        9. 8.3.4.9  BC1.2 Data Contact Detect
        10. 8.3.4.10 BC1.2 Primary and Secondary Detection
      5. 8.3.5  Power Management
        1. 8.3.5.1 Power-On and Supervisory Functions
        2. 8.3.5.2 Supply Switch-Over
        3. 8.3.5.3 RESETZ and MRESET
      6. 8.3.6  Digital Core
      7. 8.3.7  USB-PD BMC Modem Interface
      8. 8.3.8  System Glue Logic
      9. 8.3.9  Power Reset Congrol Module (PRCM)
      10. 8.3.10 Interrupt Monitor
      11. 8.3.11 ADC Sense
      12. 8.3.12 UART
      13. 8.3.13 I2C Slave
      14. 8.3.14 SPI Master
      15. 8.3.15 Single-Wire Debugger Interface
      16. 8.3.16 DisplayPort HPD Timers
      17. 8.3.17 ADC
        1. 8.3.17.1 ADC Divider Ratios
        2. 8.3.17.2 ADC Operating Modes
        3. 8.3.17.3 Single Channel Readout
        4. 8.3.17.4 Round Robin Automatic Readout
        5. 8.3.17.5 One Time Automatic Readout
      18. 8.3.18 I/O Buffers
        1. 8.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 8.3.18.2 IOBUF_OD
        3. 8.3.18.3 IOBUF_UTX
        4. 8.3.18.4 IOBUF_URX
        5. 8.3.18.5 IOBUF_PORT
        6. 8.3.18.6 IOBUF_I2C
        7. 8.3.18.7 IOBUF_GPIOHSPI
        8. 8.3.18.8 IOBUF_GPIOHSSWD
      19. 8.3.19 Thermal Shutdown
      20. 8.3.20 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Dead-Battery Condition
      5. 8.4.5 Application Code
      6. 8.4.6 Flash Memory Read
      7. 8.4.7 Invalid Flash Memory
      8. 8.4.8 UART Download
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. 8.5.2.1 I2C Interface Description
        2. 8.5.2.2 I2C Clock Stretching
        3. 8.5.2.3 I2C Address Setting
        4. 8.5.2.4 Unique Address Interface
        5. 8.5.2.5 I2C Pin Address Setting
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB Type-C and PD Dongle Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 TPS65986 External Flash
          2. 9.2.1.2.2 I2C, Debug Control (DEBUG_CTL), and SPI Resistors
          3. 9.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 9.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 9.2.1.2.5 Soft Start (SS) Capacitor
          6. 9.2.1.2.6 Port Power Switch (PP_HV and PP_5V0) Capacitors
          7. 9.2.1.2.7 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          8. 9.2.1.2.8 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 9.2.1.3 Application Curves
      2. 9.2.2 USB Type-C and PD Dock Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. 9.2.2.2.2 TPS65986 Primary and Secondary Interaction
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 TPS65986 and System Controller Interaction
          2. 9.2.3.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 9.2.3.2.3 DC Barrel Jack and Type-C PD Charging
          4. 9.2.3.2.4 Primary TPS65986 Flash Master and Secondary Port
          5. 9.2.3.2.5 TPS65986 Dead Battery Support Primary and Secondary Port
          6. 9.2.3.2.6 Debugging Methods
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 VBUS 3.3-V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
      2. 10.3.2 Schottky for Current Surge Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  TPS65986 Recommended Footprints
        1. 11.1.1.1 Standard TPS65986 Footprint (Circular Pads)
      2. 11.1.2  Alternate TPS65986 Footprint (Oval Pads)
      3. 11.1.3  Top TPS65986 Placement and Bottom Component Placement and Layout
      4. 11.1.4  Oval Pad Footprint Layout and Placement
      5. 11.1.5  Component Placement
      6. 11.1.6  Designs Rules and Guidance
      7. 11.1.7  Routing PP_HV, PP_5V0, and VBUS
      8. 11.1.8  Routing Top and Bottom Passive Components
      9. 11.1.9  Void Via Placement
      10. 11.1.10 Top Layer Routing
      11. 11.1.11 Inner Signal Layer Routing
      12. 11.1.12 Bottom Layer Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Development Support
      2. 12.1.2 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

5 Pin Configuration and Functions

ZQZ Package
96-Pin BGA
Top View

Legend for Pinout Drawing

TPS65986 pinout_legend_slvsd93.gif

Pin Functions

PIN TYPE POR STATE DESCRIPTION
NAME NO.
HIGH-CURRENT POWER PINS
PP_5V0 A11, B11, C11, D11 Power NA 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
PP_HV A6, A7, A8, B7 Power NA HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused.
PP_CABLE H10 Power NA 5-V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused.
VBUS H11, J10, J11, K11 Power NA 5-V output frm PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND.
LOW-CURRENT POWER PINS
VIN_3V3 H1 Power NA Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
VDDIO B1 Power  NA VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3. When VDDIO is not in use, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply input, bypass with capacitance CVDDIO to GND.
VOUT_3V3 H2 Power NA Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND. Float pin when unused.
LDO_3V3 G1 Power NA Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND.
LDO_1V8A K1 Power NA Output of the 3.3-V or 1.8-V LDO for core analog circuits. Bypass with capacitance CLDO_1V8A to GND.
LDO_1V8D A2 Power NA Output of the 3.3-V or 1.8-V LDO for core digital circuits. Bypass with capacitance CLDO_1V8D to GND.
LDO_BMC E1 Power NA Output of the USB-PD BMC transceiver output level LDO. Bypass with capacitance CLDO_BMC to GND.
TYPE-C PORT PINS
C_CC1 L9 Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 to GND.
C_CC2 L10 Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2 to GND.
RPD_G1 K9 Analog I/O Hi-Z Tie pin to C_CC1 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
RPD_G2 K10 Analog I/O Hi-Z Tie pin to C_CC2 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise.
C_USB_TP K6 Analog I/O Hi-Z Port-side top USB D+ connection to the port multiplexer. Tie to GND when unused.
C_USB_TN L6 Analog I/O Hi-Z Port-side top USB D– connection to the port multiplexer. Tie to GND when unused.
C_USB_BP K7 Analog I/O Hi-Z Port-side bottom USB D+ connection to the port multiplexer. Tie to GND when unused.
C_USB_BN L7 Analog I/O Hi-Z Port-side bottom USB D– connection to the port multiplexer. Tie to GND when unused.
C_SBU1 K8 Analog I/O Hi-Z Port-side sideband. Use connection of the port multiplexer. Tie to GND when unused.
C_SBU2 L8 Analog I/O Hi-Z Port-side sideband. Use connection of the port multiplexer. Tie to GND when unused.
INTERFACE PINS
SWD_DATA F4 Digital I/O Resistive pull high SWD serial data. Float pin when unused.
SWD_CLK G4 Digital input Resistive pull high SWD serial clock. Float pin when unused.
UART_RX F2 Digital input Digital input UART serial receive data. Connect pin to another TPS65986 UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65986 device and ground pin through a 100-kΩ resistance.
UART_TX E2 Digital output UART_RX UART serial transmit data. Connect pin to another TPS65986 UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65986 device.
USB_RP_P L5 Analog I/O Hi-Z System-side USB2.0 high-speed connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
USB_RP_N K5 Analog I/O Hi-Z System-side USB2.0 high-speed connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
AUX_P J1 Reserved Hi-Z System-side DisplayPort connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
AUX_N J2 Reserved Hi-Z System-side DisplayPort connection to the port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
DIGITAL CORE I/O AND CONTROL PINS
SENSEP B10 Reserved Analog input Short pin to VBUS.
SENSEN A10 Reserved Analog input Short pin to VBUS.
SS H7 Analog output Driven low Soft Start. Tie pin to capacitance CSS to ground.
R_OSC G2 Analog I/O Hi-Z External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC.
GPIO0 B2 Digital I/O Push-pull output (low) General purpose digital I/O 0. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO1 C2 Digital I/O Push-pull output (low) General purpose digital I/O 1. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO2 D10 Digital I/O Push-pull output (low) General purpose digital I/O 2. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO3 G11 Digital I/O Input (Hi-Z) General purpose digital I/O 3. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO4
(HPD TXRX)
C10 Digital I/O Input (Hi-Z) General purpose digital I/O 4. Configured as hot plug detect (HPD) TX, HPD RX, or both when DisplayPort Mode supported. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO5
(HPD RX)
E10 Digital I/O Push-pull output (low) General purpose digital I/O 5. Can be configured as HPD RX when DisplayPort Mode supported. Must be tied high or low through a 1-kΩ pull-up or pull-down resistor when used as a configuration input. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO6 G10 Digital I/O Push-pull output (low) General purpose digital I/O 6. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO7 D7 Digital I/O Push-pull output (low) General purpose digital I/O 7. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
GPIO8 H6 Digital I/O Open-drain output (Hi-Z) General purpose digital I/O 8. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
RESETZ
(GPIO9)
F11 Digital I/O Push-pull output (Low) General purpose digital I/O 9. Active-low reset output when VOUT_3V3 is low (driven low on start-up). Float pin when unused.
BUSPOWERZ
(GPIO10)
F10 Analog input Input General purpose digital I/O 10. Sampled by ADC at boot. Tie pin to LDO_3V3 through a 100-kΩ resistor to disable PP_HV power path during dead-battery or no-battery boot conditions. Refer to the BUSPOWERZ table for more details.
MRESET
(GPIO11)
E11 Digital I/O Input (Hi-Z) General purpose digital I/O 11. Forces RESETZ to assert. By default, this pin asserts RESETZ when pulled high. The pin can be programmed to assert RESETZ when pulled low. Ground pin with a 1-MΩ resistor when unused in the application.
DEBUG4
(GPIO12)
K3 Digital I/O Push-pull output (low) General purpose digital I/O 12. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
DEBUG3
(GPIO13)
L3 Digital I/O Push-pull output (low) General purpose digital I/O 13. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
DEBUG2
(GPIO14)
K2 Digital I/O Open-drain output (Hi-Z) General purpose digital I/O 14. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
DEBUG1
(GPIO15)
L2 Digital I/O Push-pull output (Low) General purpose digital I/O 15. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application.
DEBUG_CTL1 E4 Digital I/O Input (Hi-Z) General purpose digital I/O 16. Tie pin to LDO_3V3 through a 100-kΩ resistor.
DEBUG_CTL2 D5 Digital I/O Input (Hi-Z) General purpose digital I/O 17. Tie pin to LDO_3V3 through a 100-kΩ resistor.
HRESET D6 Digital I/O Input (Hi-Z) Active-high hardware reset input. Will reload settings from external flash memory. Ground pin when HRESET functionality will not be used.
I2C_SDA D1 Digital I/O Digital input I2C port serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C_SCL D2 Digital I/O Digital input I2C port serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C_IRQZ C1 Digital output Hi-Z I2C port interrupt. Active low. Implement externally as an open drain with a pull-up resistance. Float pin when unused.
I2C_ADDR F1 Analog I/O Analog input Sets the I2C address for both I2C ports as well as determine the master and slave devices for memory code sharing.
SPI_CLK A3 Digital output Digital input SPI serial clock. Connect pin directly to SPI flash when used. Ground pin when unused.
SPI_MOSI B4 Digital output Digital input SPI serial master output to slave. Connect pin directly to SPI flash when used. Ground pin when unused.
SPI_MISO A4 Digital input Digital input SPI serial master input from slave. This pin is used during boot sequence to determine if the flash memory is valid. Refer to the Boot Code section for more details. Tie pin to LDO_3V3 through a 3.3-kΩ resistor when used. Ground pin when unused.
SPI_SSZ B3 Digital output Digital input SPI slave select. Tie pin to LDO_3V3 through a 3.3-kΩ resistor when used. Ground pin when unused.
GROUND AND NO CONNECT PINS
GND A1, A5, B5, B8, D8, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8, H4, H5, H8, L1, L4 Ground NA Ground. Connect all balls to ground plane.
NC A9, B6, B9, K4, L11 Blank NA Populated ball that must remain unconnected.
No Ball C3, C4, C5, C6, C7, C8, C9, D3, D4, D9, E3, E9, F3, F9, G3, G9, H3, H9, J3, J4, J5, J6, J7, J8, J9 Blank NA Unpopulated ball for A1 marker and unpopulated inner ring.