SLVSD13C October   2015  – August 2016 TPS65986

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Power Consumption Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 USB-PD TX Driver Voltage Adjustment Parameter
    11. 6.11 Port Power Switch Characteristics
    12. 6.12 Port Data Multiplexer Switching and Timing Characteristics
    13. 6.13 Port Data Multiplexer Clamp Characteristics
    14. 6.14 Port Data Multiplexer SBU Detection Requirements
    15. 6.15 Port Data Multiplexer Signal Monitoring Pull-up and Pull-down Characteristics
    16. 6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics
    17. 6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics
    18. 6.18 Analog-to-Digital Converter (ADC) Characteristics
    19. 6.19 Input/Output (I/O) Requirements and Characteristics
    20. 6.20 I2C Slave Requirements and Characteristics
    21. 6.21 SPI Master Characteristics
    22. 6.22 Single-Wire Debugger (SWD) Timing Requirements
    23. 6.23 BUSPOWERZ Configuration Requirements
    24. 6.24 HPD Timing Requirements and Characteristics
    25. 6.25 Thermal Shutdown Characteristics
    26. 6.26 Oscillator Requirements and Characteristics
    27. 6.27 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Cable Plug and Orientation Detection
        1. 8.3.2.1 Configured as a DFP
        2. 8.3.2.2 Configured as a UFP
        3. 8.3.2.3 Dead-Battery or No-Battery Support
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1  5V Power Delivery
        2. 8.3.3.2  5V Power Switch as a Source
        3. 8.3.3.3  PP_5V0 Current Sense
        4. 8.3.3.4  PP_5V0 Current Limit
        5. 8.3.3.5  Internal HV Power Delivery
        6. 8.3.3.6  Internal HV Power Switch as a Source
        7. 8.3.3.7  Internal HV Power Switch as a Sink
        8. 8.3.3.8  Internal HV Power Switch Current Sense
        9. 8.3.3.9  Internal HV Power Switch Current Limit
        10. 8.3.3.10 Soft Start
        11. 8.3.3.11 BUSPOWERZ
        12. 8.3.3.12 Voltage Transitions on VBUS through Port Power Switches
        13. 8.3.3.13 HV Transition to PP_RV0 Pull-down on VBUS
        14. 8.3.3.14 VBUS Transition to VSAFE0V
        15. 8.3.3.15 C_CC1 and C_CC2 Power Configuration and Power Delivery
        16. 8.3.3.16 PP_CABLE to C_CC1 and C_CC2 Switch Architecture
        17. 8.3.3.17 PP_CABLE to C_CC1 and C_CC2 Current Limit
      4. 8.3.4  USB Type-C Port Data Multiplexer
        1. 8.3.4.1  USB Top and Bottom Ports
        2. 8.3.4.2  Multiplexer Connection Orientation
        3. 8.3.4.3  Digital Crossbar Multiplexer
        4. 8.3.4.4  SBU Crossbar Multiplexer
        5. 8.3.4.5  Signal Monitoring and Pull-up/Pull-down
        6. 8.3.4.6  Port Multiplexer Clamp
        7. 8.3.4.7  USB2.0 Low-Speed Endpoint
        8. 8.3.4.8  Battery Charger (BC1.2) Detection Block
        9. 8.3.4.9  BC1.2 Data Contact Detect
        10. 8.3.4.10 BC1.2 Primary and Secondary Detection
      5. 8.3.5  Power Management
        1. 8.3.5.1 Power-On and Supervisory Functions
        2. 8.3.5.2 Supply Switch-Over
        3. 8.3.5.3 RESETZ and MRESET
      6. 8.3.6  Digital Core
      7. 8.3.7  USB-PD BMC Modem Interface
      8. 8.3.8  System Glue Logic
      9. 8.3.9  Power Reset Congrol Module (PRCM)
      10. 8.3.10 Interrupt Monitor
      11. 8.3.11 ADC Sense
      12. 8.3.12 UART
      13. 8.3.13 I2C Slave
      14. 8.3.14 SPI Master
      15. 8.3.15 Single-Wire Debugger Interface
      16. 8.3.16 DisplayPort HPD Timers
      17. 8.3.17 ADC
        1. 8.3.17.1 ADC Divider Ratios
        2. 8.3.17.2 ADC Operating Modes
        3. 8.3.17.3 Single Channel Readout
        4. 8.3.17.4 Round Robin Automatic Readout
        5. 8.3.17.5 One Time Automatic Readout
      18. 8.3.18 I/O Buffers
        1. 8.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C
        2. 8.3.18.2 IOBUF_OD
        3. 8.3.18.3 IOBUF_UTX
        4. 8.3.18.4 IOBUF_URX
        5. 8.3.18.5 IOBUF_PORT
        6. 8.3.18.6 IOBUF_I2C
        7. 8.3.18.7 IOBUF_GPIOHSPI
        8. 8.3.18.8 IOBUF_GPIOHSSWD
      19. 8.3.19 Thermal Shutdown
      20. 8.3.20 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot Code
      2. 8.4.2 Initialization
      3. 8.4.3 I2C Configuration
      4. 8.4.4 Dead-Battery Condition
      5. 8.4.5 Application Code
      6. 8.4.6 Flash Memory Read
      7. 8.4.7 Invalid Flash Memory
      8. 8.4.8 UART Download
    5. 8.5 Programming
      1. 8.5.1 SPI Master Interface
      2. 8.5.2 I2C Slave Interface
        1. 8.5.2.1 I2C Interface Description
        2. 8.5.2.2 I2C Clock Stretching
        3. 8.5.2.3 I2C Address Setting
        4. 8.5.2.4 Unique Address Interface
        5. 8.5.2.5 I2C Pin Address Setting
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 USB Type-C and PD Dongle Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 TPS65986 External Flash
          2. 9.2.1.2.2 I2C, Debug Control (DEBUG_CTL), and SPI Resistors
          3. 9.2.1.2.3 Oscillator (R_OSC) Resistor
          4. 9.2.1.2.4 VBUS Capacitor and Ferrite Bead
          5. 9.2.1.2.5 Soft Start (SS) Capacitor
          6. 9.2.1.2.6 Port Power Switch (PP_HV and PP_5V0) Capacitors
          7. 9.2.1.2.7 Cable Connection (CCn) Capacitors and RPD_Gn Connections
          8. 9.2.1.2.8 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, and VDDIO
        3. 9.2.1.3 Application Curves
      2. 9.2.2 USB Type-C and PD Dock Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Port Power Switch (PP_5V0 and PP_CABLE) Capacitors
          2. 9.2.2.2.2 TPS65986 Primary and Secondary Interaction
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 TPS65986 and System Controller Interaction
          2. 9.2.3.2.2 HD3SS460 Control and DisplayPort Configuration
          3. 9.2.3.2.3 DC Barrel Jack and Type-C PD Charging
          4. 9.2.3.2.4 Primary TPS65986 Flash Master and Secondary Port
          5. 9.2.3.2.5 TPS65986 Dead Battery Support Primary and Secondary Port
          6. 9.2.3.2.6 Debugging Methods
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3 V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
      3. 10.1.3 VBUS 3.3-V LDO
    2. 10.2 1.8 V Core Power
      1. 10.2.1 1.8 V Digital LDO
      2. 10.2.2 1.8 V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
      2. 10.3.2 Schottky for Current Surge Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  TPS65986 Recommended Footprints
        1. 11.1.1.1 Standard TPS65986 Footprint (Circular Pads)
      2. 11.1.2  Alternate TPS65986 Footprint (Oval Pads)
      3. 11.1.3  Top TPS65986 Placement and Bottom Component Placement and Layout
      4. 11.1.4  Oval Pad Footprint Layout and Placement
      5. 11.1.5  Component Placement
      6. 11.1.6  Designs Rules and Guidance
      7. 11.1.7  Routing PP_HV, PP_5V0, and VBUS
      8. 11.1.8  Routing Top and Bottom Passive Components
      9. 11.1.9  Void Via Placement
      10. 11.1.10 Top Layer Routing
      11. 11.1.11 Inner Signal Layer Routing
      12. 11.1.12 Bottom Layer Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Development Support
      2. 12.1.2 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage(2) PP_CABLE, PP_5V0 –0.3 6 V
VIN_3V3 –0.3 3.6
SENSEP, SENSEN –0.3 24
VDDIO, UART_RX –0.3 LDO_3V3 + 0.3
VIO Output voltage(2) LDO_1V8A, LDO_1V8D, LDO_BMC, SS –0.3 2 V
LDO_3V3 –0.3 3.45
VOUT_3V3, RESETZ, I2C_IRQZ, SPI_MOSI, SPI_CLK, SPI_SSZ, SWD_CLK, UART_TX –0.3 LDO_3V3 + 0.3
VIO I/O voltage(2) PP_HV, VBUS –0.3 24 V
I2C_SDA, I2C_SCL, SWD_DATA, SPI_MISO, USB_RP_P, USB_RP_N, AUX_N, AUX_P, DEBUG1, DEBUG2, DEBUG3, DEBUG4, DEBUG_CTL1, DEBUG_CTL2, GPIOn, MRESET, BUSPOWERZ, GPIO0-8 –0.3 LDO_3V3 + 0.3
R_OSC, I2C_ADDR –0.3 2
HRESET –0.3 LDO_1V8D + 0.3
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (Switches Open) –2 6
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (Switches Closed) –0.3 6
C_CC1, C_CC2, RPD_G1, RPD_G2 –0.3 6
TJ Operating junction temperature –10 125 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Input voltage(1) VIN_3V3 2.85 3.45 V
PP_5V0 4.75 5.5
PP_CABLE 2.95 5.5
PP_HV 4.5 22
VDDIO 1.7 3.45
VIO I/O voltage(1) VBUS 4 22 V
C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU1, C_SBU2 –2 5.5
C_CC1, C_CC2 0 5.5
TA Ambient operating temperature –10 85 °C
TB Operating board temperature –10 100 °C
TJ Operating junction temperature –10 125 °C
(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

6.4 Thermal Information

THERMAL METRIC(1) TPS65986 UNIT
ZQZ (BGA MicroStar Junior)
96 PIN
RθJA Junction-to-ambient thermal resistance 42.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 12.4 °C/W
RθJB Junction-to-board thermal resistance 13 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 13 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Supply Requirements and Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL
VIN_3V3 Input 3.3-V supply 2.85 3.3 3.45 V
PP_CABLE Input voltage to power C_CC pins. This input is also available to power core circuitry and the VOUT_3V3 output 2.95 5 5.5 V
VBUS Bi-direction DC bus voltage. Output from the TPS65986 or input to the TPS65986 4 5 22 V
PP_5V0 5V supply input to power VBUS. This supply does not power the TPS65986 4.75 5 5.5 V
VDDIO(1) Optional supply for I/O cells. 1.7 3.45 V
INTERNAL
VLDO_3V3 DC 3.3V generated internally by either a switch from VIN_3V3, an LDO from PP_CABLE, or an LDO from VBUS 2.7 3.3 3.45 V
VDO_LDO3V3 Drop Out Voltage of LDO_3V3 from PP_CABLE ILOAD = 50 mA 250 mV
Drop Out Voltage of LDO_3V3 from VBUS 250 500 750 mV
VLDO_1V8D DC 1.8 V generated for internal digital circuitry 1.7 1.8 1.9 V
VLDO_1V8A DC 1.8 V generated for internal analog circuitry 1.7 1.8 1.9 V
VLDO_BMC DC voltage generated on LDO_BMC. Setting for USB-PD 1.05 1.125 1.2 V
ILDO_3V3 DC current supplied by the 3.3-V LDOs. This includes internal core power and external load on LDO_3V3. 70 mA
ILDO_3V3EX External DC current supplied by LDO_3V3 30 mA
IOUT_3V3 External DC current supplied by VOUT_3V3 100 mA
ILDO_1V8D DC current supplied by LDO_1V8D. This is intended for internal loads only but small external loads may be added 50 mA
ILDO_1V8DEX External DC current supplied by LDO_1V8D 5 mA
ILDO_1V8A DC current supplied by LDO_1V8A. This is intended for internal loads only but small external loads may be added 20 mA
ILDO_1V8AEX External DC current supplied by LDO_1V8A 5 mA
ILDO_BMC DC current supplied by LDO_BMC. This is intended for internal loads only 5 mA
ILDO_BMCEX External DC current supplied by LDO_BMC 0 mA
VFWD_DROP Forward voltage drop across VIN_3V3 to LDO_3V3 switch ILOAD = 50 mA 25 60 90 mV
RIN_3V3 Input switch resistance from VIN_3V3 to LDO_3V3 VVIN_3V3 – VLDO_3V3 > 50 mV 0.5 1.1 1.75 Ω
ROUT_3V3 Output switch resistance from VIN_3V3 to VOUT_3V3 0.35 0.7 Ω
TR_OUT3V3 10% - 90% rise time on VOUT_3V3 from switch enable CVOUT_3V3 = 1 μF 35 120 µs
(1) I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3, the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high.

6.6 Power Supervisor Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UV_LDO3V3 Undervoltage threshold for LDO_3V3. Locks out 1.8-V LDOs LDO_3V3 rising 2.2 2.325 2.45 V
UVH_LDO3V3 Undervoltage hysteresis for LDO_3V3 LDO_3V3 falling 20 80 150 mV
UV_VBUS_LDO Undervoltage threshold for VBUS to enable LDO VBUS rising 3.35 3.75 3.95 V
UVH_VBUS_LDO Undervoltage hysteresis for VBUS to enable LDO VBUS falling 20 80 150 mV
UV_PCBL Undervoltage threshold for PP_CABLE PP_CABLE rising 2.5 2.625 2.75 V
UVH_PCBL Undervoltage hysteresis for PP_PCABLE PP_CABLE falling 20 50 80 mV
UV_5V0 Undervoltage threshold for PP_5V0 PP_5V0 rising 3.5 3.725 3.95 V
UVH_5V0 Undervoltage hysteresis for PP_P5V0 PP_5V0 falling 20 80 150 mV
OV_VBUS Overvoltage threshold for VBUS. This value is a 6-bit programmable threshold VBUS rising 5 24 V
OVLSB_VBUS Overvoltage threshold step for VBUS. This value is the LSB of the programmable threshold VBUS rising 328 mV
OVH_VBUS Overvoltage hysteresis for VBUS VBUS falling, % of OV_VBUS 0.9% 1.3% 1.7%
UV_VBUS Undervoltage threshold for VBUS. This value is a 6-bit programmable threshold VBUS falling 2.5 18.21 V
UVLSB_VBUS Undervoltage threshold step for VBUS. This value is the LSB of the programmable threshold VBUS falling 249 mV
UVH_VBUS Undervoltage hysteresis for VBUS VBUS rising, % of UV_VBUS 0.9% 1.3% 1.7%
UVR_OUT3V3 Configurable undervoltage threshold for VOUT_3V3 rising. De-asserts RESETZ Setting 0 2.019 2.125 2.231 V
Setting 1 2.138 2.25 2.363
Setting 2 2.256 2.375 2.494
Setting 3 2.375 2.5 2.625
Setting 4 2.494 2.625 2.756
Setting 5 2.613 2.75 2.888
Setting 6 2.731 2.875 3.019
Setting 7 2.85 3 3.15
UVRH_OUT3V3 Undervoltage hysteresis for VOUT_3V3 falling. OUT_3V3 falling 30 50 mV
TUVRASSERT Delay from falling VOUT_3V3 or MRESET assertion to RESETZ asserting low 75 μs
TUVRDELAY Configurable delay from VOUT_3V3 to RESETZ deassertion 0 161.3 ms

6.7 Power Consumption Characteristics

Recommended operating conditions; TA = 25°C (Room temperature) unless otherwise noted(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVIN_3V3 Sleep(1) VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, PPCABLE = 0; 100-kHz Oscillator running 58 µA
Idle (2) VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE= 0; 100-kHz Oscillator running,
48-MHz Oscillator running
1.66 mA
Active(3) VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE= 0; 100-kHz Oscillator running,
48-MHz Oscillator running
5.64 mA
(1) Sleep is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active.
(2) Idle is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, and a selectable clock to the digital core of 3 MHz or 4 MHz.
(3) Active is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, all core functionality active, and the digital core is clocked at 12 MHz.
(4) Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code also provisions the wake=up mechanisms (for example, I2C activity and GPIO activity).

6.8 Cable Detection Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IH_CC_USB Source Current through each C_CC pin when in a disconnected state and Configured as a DFP advertising Default USB current to a peripheral device 73.6 80 86.4 μA
IH_CC_1P5 Source Current through each C_CC pin when in a disconnected state when Configured as a DFP advertising 1.5 A to a UFP 169 180 191 μA
IH_CC_3P0 Source Current through each C_CC pin when in a disconnected state and Configured as a DFP advertising 3.0 A to a UFP. VIN_3V3 ≥ 3.135 V 303 330 356 μA
VD_CCH_USB Voltage Threshold for detecting a DFP attach when configured as a UFP and the DFP is advertising Default USB current source capability 0.15 0.2 0.25 V
VD_CCH_1P5 Voltage Threshold for detecting a DFP advertising 1.5 A source capability when configured as a UFP 0.61 0.66 0.7 V
VD_CCH_3P0 Voltage Threshold for detecting a DFP advertising 3 A source capability when configured as a UFP 1.169 1.23 1.29 V
VH_CCD_USB Voltage Threshold for detecting a UFP attach when configured as a DFP and advertising Default USB current source capability IH_CC = IH_CC_USB 1.473 1.55 1.627 V
VH_CCD_1P5 Voltage Threshold for detecting a UFP attach when configured as a DFP and advertising 1.5 A source capability IH_CC = IH_CC_1P5 1.473 1.55 1.627 V
VH_CCD_3P0 Voltage Threshold for detecting a UFP attach when configured as a DFP and advertising 3.0 A source capability IH_CC = IH_CC_3P0
VIN_3V3 ≥ 3.135 V
2.423 2.55 2.67 V
VH_CCA_USB Voltage Threshold for detecting an active cable attach when configured as a DFP and advertising Default USB current capability 0.15 0.2 0.25 V
VH_CCA_1P5 Voltage Threshold for detecting active cables attach when configured as a DFP and advertising 1.5 A capability 0.35 0.4 0.45 V
VH_CCA_3P0 Voltage Threshold for detecting active cables attach when configured as a DFP and advertising 3 A capability. 0.76 0.8 0.84 V
RD_CC Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP. LDO_3V3 powered V = 1 V, 1.5 V 4.85 5.1 5.35
RD_CC_OPEN Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP. LDO_3V3 powered V = 0 V to LDO_3V3 500
RD_DB Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP when configured for dead battery (RPD_Gn tied to C_CCn). LDO_3V3 unpowered V = 1.5 V, 2.0 V
RPD_Gn tied to C_CCn
4.08 5.1 6.12
RD_DB_OPEN Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP when not configured for dead battery (RPD_Gn tied to GND). LDO_3V3 unpowered V = 1.5 V, 2.0 V
RPD_Gn tied to GND
500
VTH_DB Threshold Voltage of the pull-down FET in series with RD during dead battery I_CC = 80 μA 0.5 0.9 1.2 V
R_RPD Resistance between RPD_Gn and the gate of the pull-down FET 25 50 85

6.9 USB-PD Baseband Signal Requirements and Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON
PD_BITRATE PD data bit rate 270 300 330 Kbps
UI(1) Unit interval (1/PD_BITRATE) 3.03 3.33  3.7 μs
CCBLPLUG(2) Capacitance for a cable plug (each plug on a cable may have up to this value) 25 pF
ZCABLE Cable characteristic impedance 32 65 Ω
CRECEIVER(3) Receiver capacitance. Capacitance looking into C_CCn pin when in receiver mode.  70 120 pF
TRANSMITTER
ZDRIVER TX output impedance. Source output impedance at the Nyquist frequency of USB2.0 low speed (750 kHz) while the source is driving the C_CCn line. 33 75 Ω
TRISE Rise Time. 10% to 90% amplitude points, minimum is under an unloaded condition. Maximum set by TX mask. 300 ns
TFALL Fall Time. 90% to 10% amplitude points, minimum is under an unloaded condition. Maximum set by TX mask. 300 ns
RECEIVER
VRXTR Rx Receive Rising Input threshold 605 630 655 mV
VRXTF Rx Receive Falling Input threshold 450  470 490 mV
NCOUNT(4) Number of transitions for signal detection (number to count to detect non-idle bus). 3
TTRANWIN(4) Time window for detecting non-idle bus. 12 20 μs
ZBMCRX Receiver input impedance Does not include pull-up or pull-down resistance from cable detect. Transmitter is Hi-Z. 10
TRXFILTER(5) Rx bandwidth limiting filter. Time constant of a single pole filter to limit broadband noise ingression 100 ns
(1) UI denotes the time to transmit an un-encoded data bit not the shortest high or low times on the wire after encoding with BMC. A single data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the transition at the start of the cell.
(2) The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.
(3) CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. It is recommended to add capacitance to bring the total pin capacitance to 300 pF for improved TX behavior.
(4) BMC packet collision is avoided by the detection of signal transitions at the receiver. Detection is active when a minimum of NCOUNT transitions occur at the receiver within a time window of TTRANWIN. After waiting TTRANWIN without detecting NCOUNT transitions, the bus is declared idle.
(5) Broadband noise ingression is due to coupling in the cable interconnect.

6.10 USB-PD TX Driver Voltage Adjustment Parameter(1)

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER MIN NOM MAX UNIT
VTXP0 TX Transmit Peak Voltage 1.615 1.7 1.785 V
VTXP1 TX Transmit Peak Voltage 1.52 1.6 1.68 V
VTXP2 TX Transmit Peak Voltage 1.425 1.5 1.575 V
VTXP3 TX Transmit Peak Voltage 1.33 1.4 1.47 V
VTXP4 TX Transmit Peak Voltage 1.235 1.3 1.365 V
VTXP5 TX Transmit Peak Voltage 1.188 1.25 1.312 V
VTXP6 TX Transmit Peak Voltage 1.14 1.2 1.26 V
VTXP7 TX Transmit Peak Voltage 1.116 1.175 1.233 V
VTXP8 TX Transmit Peak Voltage 1.092 1.15 1.208 V
VTXP9 TX Transmit Peak Voltage 1.068 1.125 1.181 V
VTXP10 TX Transmit Peak Voltage 1.045 1.1 1.155 V
VTXP11 TX Transmit Peak Voltage 1.021 1.075 1.128 V
VTXP12 TX Transmit Peak Voltage 0.998 1.05 1.102 V
VTXP13 TX Transmit Peak Voltage 0.974 1.025 1.076 V
VTXP14 TX Transmit Peak Voltage 0.95 1 1.05 V
VTXP15 TX Transmit Peak Voltage 0.903 0.95 0.997 V
(1) VTXP voltage settings are determined by application code and the setting used must meet the needs of the application and adhere to the USB-PD Specifications.

6.11 Port Power Switch Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT
RPPCC PP_CABLE to C_CCn power switch resistance 312
RPP5V PP_5V0 to VBUS power switch resistance 50 60
RPPHV PP_HV to VBUS power switch resistance 95 135
IHVACT Active quiescent current from PP_HV pin, EN_HV = 1 1 mA
IHVSD Shutdown quiescent current from PP_HV pin, EN_HV = 0 100 μA
IHVEXTACT Active quiescent current from SENSEP pin, EN_HV = 1 Configured as source 1 mA
Active quiescent current from VBUS pin, EN_HV = 1 Configured as sink 3.5 mA
IHVEXTSD Shutdown quiescent current from SENSEP pin, EN_HV = 0 40 μA
IPP5VACT Active quiescent current from PP_5V0 1 mA
IPP5VSD Shutdown quiescent current from PP_5V0 100 μA
ILIMHV(3) PP_HV current limit, setting 0 1.007 1.118 1.330 A
PP_HV current limit, setting 1 1.258 1.398 1.638 A
PP_HV current limit, setting 2 1.51 1.678 1.945 A
PP_HV current limit, setting 3 1.761 1.957 2.153 A
PP_HV current limit, setting 4 2.013 2.237 2.46 A
PP_HV current limit, setting 5 2.265 2.516 2.768 A
PP_HV current limit, setting 6 2.516 2.796 3.076 A
PP_HV current limit, setting 7 2.768 3.076 3.383 A
PP_HV current limit, setting 8 3.02 3.355 3.691 A
PP_HV current limit, setting 9 3.271 3.635 3.998 A
PP_HV current limit, setting 10 3.523 3.914 4.306 A
PP_HV current limit, setting 11 3.775 4.194 4.613 A
PP_HV current limit, setting 12 4.026 4.474 4.921 A
PP_HV current limit, setting 13 4.278 4.753 5.228 A
PP_HV current limit, setting 14 4.529 5.033 5.536 A
PP_HV current limit, setting 15 5.033 5.592 6.151 A
ILIMPP5V(3) PP_5V0 current limit, setting 0 1.006 1.118 1.330 A
PP_5V0 current limit, setting 1 1.132 1.258 1.484 A
PP_5V0 current limit, setting 2 1.258 1.398 1.638 A
PP_5V0 current limit, setting 3 1.384 1.538 1.691 A
PP_5V0 current limit, setting 4 1.51 1.677 1.845 A
PP_5V0 current limit, setting 5 1.636 1.817 1.999 A
PP_5V0 current limit, setting 6 1.761 1.957 2.153 A
PP_5V0 current limit, setting 7 1.887 2.097 2.307 A
PP_5V0 current limit, setting 8 2.013 2.237 2.46 A
PP_5V0 current limit, setting 9 2.139 2.376 2.614 A
PP_5V0 current limit, setting 10 2.265 2.516 2.768 A
PP_5V0 current limit, setting 11 2.39 2.656 2.922 A
PP_5V0 current limit, setting 12 2.516 2.796 3.075 A
PP_5V0 current limit, setting 13 2.642 2.936 3.229 A
PP_5V0 current limit, setting 14 2.768 3.075 3.383 A
PP_5V0 current limit, setting 15 3.019 3.355 3.69 A
ILIMPPCC PP_CABLE current limit (highest setting) 0.6 0.75 0.9 A
PP_CABLE current limit (lowest setting) 0.35 0.45 0.55 A
IHV_ACC(1) PP_HV current sense accuracy  I = 100 mA Reverse current blocking disabled 3.25 5 6.75 A/V
 I = 200 mA 4 5 6 A/V
 I = 500 mA 4.4 5 5.6 A/V
 I ≥ 1 A 4.5 5 5.5 A/V
IPP5V_ACC(1) PP_5V0 current sense accuracy  I = 100 mA Reverse current blocking disabled 1.95 3 4.05 A/V
 I = 200 mA 2.4 3 3.6 A/V
 I = 500 mA 2.64 3 3.36 A/V
 I ≥ 1 A 2.7 3 3.3 A/V
IPPCBL_ACC PP_CABLE current sense accuracy  I = 100 mA - 1 - A/V
 I = 200 mA - 1 - A/V
 I = 500 mA - 1 - A/V
TON_HV PP_HV path turn on time from enable to VBUS = 95% of PP_HV voltage Configured as a source or as a sink with soft start disabled. PP_HV = 20 V, CVBUS = 10 μF, ILOAD = 100 mA 8 ms
TON_5V PP_5V0 path turn on time from enable to VBUS = 95% of PP_5V0 voltage Configured as a source or as a sink with soft start disabled. PP_5V0 = 5 V, CVBUS = 10 μF, ILOAD = 100 mA 2.5 ms
TON_CC PP_CABLE path turn on time from enable to C_CCn = 95% of the PP_CABLE voltage PP_CABLE = 5 V, C_CCn = 500 nF, ILOAD = 100 mA 2 ms
ISS Soft start charging current 5.5 7 8.5 μA
RSS_DIS Soft start discharge resistance 0.6 1 1.4
VTHSS Soft start complete threshold 1.35 1.5 1.65 V
TSSDONE Soft start complete time CSS = 220 nF 31.9 46.2 60.5 ms
VREVPHV Reverse current blocking voltage threshold for PP_HV switch 2 6 10 mV
VREV5V0 Reverse current blocking voltage threshold for PP_5V0 switches 2 6 10 mV
VHVDISPD Voltage threshold above VIN at which the pull-down RHVDISPD on VBUS will disable during a transition from PHV to 5V0 45 200 250 mV
VSAFE0V Voltage that is a safe 0V per USB-PD Specifications 0 0.8 V
TSAFE0V Voltage transition time to VSAFE0V 650 ms
VSO_HV Voltage on PP_HV above which the PP_HV to PP_5V0 transition on VBUS will meet transition requirements 9.9 V
SRPOS Maximum slew rate for positive voltage transitions 0.03 V/μs
SRNEG Maximum slew rate for negative voltage transitions –0.03 V/μs
TSTABLE EN to stable time for both positive and negative voltage transitions 275 ms
VSRCVALID Supply Output Tolerance beyond VSRCNEW during time TSTABLE –0.5 0.5 V
VSRCNEW Supply Output Tolerance –5 5 %
(1) The current sense in the ADC will not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV due to the reverse blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.
(2) Maximum capacitance on VBUS when configured as a source must not exceed 12 µF.
(3) Settings selected automatically by application code for the current limit needed in the application.

6.12 Port Data Multiplexer Switching and Timing Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUX MULTIPLEXER PATH(1)
AUX_RON On resistance of AUX_P/N to C_SBU1/2 Vi = 3.3 V, IO = 20 mA 3.5 7 Ω
Vi = 1 V, IO = 20 mA 2.5 5
AUX_ROND On resistance difference between P and N paths of AUX_P/N to C_SBU1/2 Vi = 1 V to 3.3 V, IO = 20 mA –0.25 0.25 Ω
AUX_TON Switch on time from enable of AUX_P/N to C_SBU1/2 Time from enable bit with charge pump off 150 μs
Time from enable bit at charge pump steady state 15
AUX_TOFF Switch off time from disable of AUX_P/N to C_SBU1/2 Time from disable bit at charge pump steady state 500 ns
AUX_BW 3dB bandwidth of AUX_P/N to C_SBU1/2 path CL = 10 pF 200 MHz
UART MULTIPLEXER PATH (2nd Stage Only)(1)(2)
UART_RON On resistance of UART buffers to C_USB_TP/TN/BP/BN or C_SBU1/2 Vi = 3.3 V, IO = 20 mA 3.1 12 Ω
UART_TON Switch on time from enable of UART buffer C_USB_TP/TN/BP/BN or C_SBU1/2 path Time from enable bit with charge pump off 150 µs
Time from enable bit at charge pump steady state 10
UART_TOFF Switch off time from disable of UART buffer path Time from disable bit at charge pump steady state 500 ns
UART_BW 3dB bandwidth of UART buffer path CL = 10 pF 200 MHz
USB_RP MULTIPLEXER PATH(1)(3)
USB_RON On resistance of USB_RP to C_USB_TP/TN/BP/BN Vi = 3 V, IO = 20 mA 4.5 10 Ω
Vi = 400 mV, IO = 20 mA 3 7
USB_ROND On resistance difference between P and N paths of USB_RP to C_USB_TP/TN/BP/BN Vi = 0.4 V to 3 V, IO = 20 mA –0.15 0.15 Ω
USB_TON Switch on time from enable of USB USB_RP path Time from enable bit with charge pump off 150 µs
Time from enable bit at charge pump steady state 15
USB_TOFF Switch off time from disable of USB_RP path Time from disable bit at charge pump steady state 500 ns
USB_BW 3dB bandwidth of USB_RP path CL = 10 pF 850 MHz
USB_ISO Off Isolation of USB_RP path RL = 50 Ω, VI = 800 mV, f = 240 MHz –19 dB
USB_XTLK Channel to Channel crosstalk of USB_RP path RL = 50 Ω, f = 240 MHz –26 dB
C_SBU1/2 OUTPUT
R_SBU_OPEN Resistance of the open C_SBU1/2 paths Vi = 0 V to LDO_3V3 1
R_USB_OPEN Resistance of the open C_USB_T/B/P/N paths Vi = 0 V to LDO_3V3 1
(1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum difference between the two switches in a pair. ROND does not add to RON.
(2) The UART switch path connects from the UART buffers to the port pins. See Input/Output (I/O) Requirements and Characteristics for buffer specifications.

6.13 Port Data Multiplexer Clamp Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCLMP_IND Clamp Voltage triggering indicator to Digital Core 3.8 3.95 4.1 V
ICLMP_IND Clamp Current at VCLMP_IND 10 250 μA
TCLMP_PRT(1) Time from clamp current crossing ICLMP_IND to interrupt signal assertion I ≥ ICLMP_IND rising 0 4 μs
ICLMP USB_EP and USB_RP Port Clamp Current V = LDO_3V3 250 nA
V = VCLMP_IND + 500 mV 3.5 15 mA
(1) The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time may be longer.

6.14 Port Data Multiplexer SBU Detection Requirements

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH_PORT Port switch detect input high voltage LDO_3V3 = 3.3 V 2.0 V
VIL_PORT Port switch detect input low voltage LDO_3V3 = 3.3 V 0.8 V

6.15 Port Data Multiplexer Signal Monitoring Pull-up and Pull-down Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RPU05 500-Ω pull-up/pull-down resistance LDO_3V3 = 3.3 V 350 500 650 Ω
RTPU5 5-kΩ pull-up/pull-down resistance LDO_3V3 = 3.3 V 3.5 5 6.5
RPU100 100-kΩ pull-up/pull-down resistance LDO_3V3 = 3.3 V 70 100 130

6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Transmitter(1)
T_RISE_EP Rising transition time Low-speed (1.5 Mbps) data rate only 75 300 ns
T_FALL_EP Falling transition time Low-speed (1.5 Mbps) data rate only 75 300 ns
T_RRM_EP Rise/Fall time matching Low-speed (1.5 Mbps) data rate only –20% 25%
V_XOVER_EP Output crossover voltage 1.3 2 V
RS_EP Source resistance of driver including 2nd Stage Port Data Multiplexer 34 Ω
Differential Receiver(1)
VOS_DIFF_EP Input offset –100 100 mV
VIN_CM_EP Common Mode Range 0.8 2.5 V
RPU_EP D– Bias Resistance Receiving 1.425 1.575
Single Ended Receiver(1)
VTH_SE_EP Single ended threshold Signal rising/falling 0.8 2 V
VHYS_SE_EP Single ended threshold hysteresis Signal falling 200 mV
(1) The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for VIN_3V3 ≥ 3.135 V

6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data Contact Detect
IDP_SRC DCD Source Current LDO_3V3 = 3.3 V 7 10 13 μA
RDM_DWN DCD pull-down resistance 14.25 20 24.8
VLGC_HI Threshold for no connection VC_USB_TP/BP ≥ VLGC_HILDO_3V3 = 3.3 V
LDO_3V3 = 3.3 V
2 V
VLGC_LO Threshold for connection VC_USB_TP/BP ≤ VLGC_LO
LDO_3V3 = 3.3 V
0.8 V
Primary and Secondary Detect
VDX_SRC Source voltage 0.55 0.6 0.65 V
VDX_RSRC Total series resistance due to Port Data Multiplexer VDX_SRC = 0.65 V 65 Ω
VDX_ILIM VDX_SRC current limit 250 400 μA
IDX_SNK Sink Current VC_USB_TN/BN ≥ 250 mV 25 75 125 μA

6.18 Analog-to-Digital Converter (ADC) Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER MIN TYP MAX UNIT
RES_ADC ADC Resolution 10 bits
F_ADC ADC clock frequency 1.477 1.5 1.523 MHz
T_ENA ADC enable time 42.14 43 43.86 μs
T_SAMPLEA ADC input sample time 10.5 10.67 10.9 μs
T_CONVERTA ADC conversion time 7.88 8 8.12 μs
T_INTA ADC interrupt time 1.31 1.33 1.35 μs
LSB Least Significant Bit 1.152 1.17 1.188 mV
DNL Differential Non-linearity –0.65 0.65 LSB
INL Integral Non-linearity –1.2 1.2 LSB
GAIN_ERR Gain Error (divider) –1.5% 1.5%
Gain Error (no divider) –1 1
VOS_ERR Buffer Offset Error –10 10 mV
THERM_ACC Thermal Sense Accuracy –8 8 °C
THERM_GAIN Thermal slope 3.095 mV/°C
THERM_V0 Zero Degree Voltage 0.823 V

6.19 Input/Output (I/O) Requirements and Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SPI
SPI_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V
SPI_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V
SPI_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2 V
SPI_ILKG Leakage Current Output is Hi-Z, VIN = 0 to LDO_3V3  –1 1 μA
SPI_VOH SPI Output High Voltage IO =  –8 mA, LDO_3V3 = 3.3 V 2.9 V
IO =  –15 mA, LDO_3V3 = 3.3 V 2.5
SPI_VOL SPI Output Low Voltage IO = 10 mA 0.4 V
IO = 20 mA 0.8
SWDIO
SWDIO_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V
SWDIO_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V
SWDIO_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2 V
SWDIO_ILKG Leakage Current Output is Hi-Z, VIN = 0 to LDO_3V3  –1 1 μA
SWDIO_VOH Output High Voltage IO =  –8 mA, LDO_3V3 = 3.3 V 2.9 V
IO =  –15 mA, LDO_3V3 = 3.3 V 2.5
SWDIO_VOL Output Low Voltage IO = 10 mA 0.4 V
IO = 20 mA 0.8
SWDIO_RPU Pull-up Resistance 2.8 4 5.2
SWDIO_TOS SWDIO Output skew to falling edge SWDCLK  –5 5 ns
SWDIO_TIS Input Setup time required between SWDIO and rising edge of SWCLK 6 ns
SWDIO_TIH Input Hold time required between SWDIO and rising edge of SWCLK 1 ns
SWDCLK
SWDCL_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V
SWDCL_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V
SWDCL_THI SWDIOCLK HIGH period 0.05 500 μs
SWDCL_TLO SWDIOCLK LOW period 0.05 500 μs
SWDCL_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2  V
SWDCL_RPU Pull-up Resistance 2.8 4 5.2
GPIO (GPIO0-8, DEBUG1-4, DEBUG_CTL1/2, MRESET, RESETZ, BUSPOWERZ)
GPIO_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V
VDDDIO = 1.8 V 1.25
GPIO_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V
VDDIO = 1.8 V 0.63
GPIO_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2  V
VDDIO = 1.8 V 0.09
GPIO_ILKG I/O Leakage Current Pin is Hi-Z;
VIN = 0 V to VDD (VDDIO or LDO_3V3)
 –1 1 μA
GPIO_RPU Pull-up resistance (GPIO0-8, DEBUG1-4, MRESET, RESETZ, BUSPOWERZ) Pull-up enabled  50 100 150
Pull-up resistance (DEBUG_CTL1/2) Pull-up enabled 2.5 5 7.5
GPIO_RPD Pull-down resistance (GPIO0-8, DEBUG1-4, MRESET, RESETZ, BUSPOWERZ) (1) Pull-down enabled 50  100 150
GPIO_DG Digital input path de-glitch 20 ns
GPIO_VOH GPIO Output High Voltage IO = –2 mA, LDO_3V3 = 3.3 V 2.9 V
IO = –2 mA, VDDIO = 1.8 V 1.35
GPIO_VOL GPIO Output Low Voltage IO = 2 mA, LDO_3V3 = 3.3 V 0.4 V
IO = 2 mA, VDDIO = 1.8 V 0.45
HRESET
HRESET_VIH High-level input voltage 1.25 V
HRESET_VIL Low-level input voltage 0.63 V
HRESET_HYS Input hysteresis Voltage 0.09 V
HRESET_ILKG I/O leakage current VIN = 0 V to LDO_1V8D  –1 1 μA
HRESET_THIGH HRESET minimum high time to assert a reset condition 2.0 ms
HRESET_TLOW HRESET minimum low time to de-assert a reset condition 2.0
UART_RX/TX
UARTRX_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V
VDDDIO = 1.8 V 1.25
UARTRX_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V
VDDIO = 1.8 V 0.63
UARTRX_HYS Input hysteresis Voltage LDO_3V3 = 3.3 V 0.2 V
VDDIO = 1.8 V 0.09
UARTTX_VOH GPIO Output High Voltage IO = –2 mA, LDO_3V3 = 3.3 V 2.9 V
IO = –2 mA, VDDIO = 1.8 V 1.35
UARTTX_VOL GPIO Output Low Voltage IO = 2 mA, LDO_3V3 = 3.3 V 0.4 V
IO = 2 mA, VDDIO = 1.8 V 0.45
UARTTX_RO Output impedance, TX channel  LDO_3V3 = 3.3 V  35 70 115 Ω
UARTTX_TRTF Rise and fall time, TX channel 10%–90%, CL = 20 pF 1 40 ns
UART_FMAX Maximum UART baud rate 1.1 Mbps
I2C_IRQZ
OD_VOL Low level output voltage IOL = 2 mA 0.4 V
OD_LKG Leakage Current Output is Hi-Z, VIN = 0 to LDO_3V3  –1 1 μA
SBU
SBU_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 V
SBU_VIL Low Input Voltage LDO_3V3 = 3.3 V 0.8 V
SBU_HYS Input hysteresis Voltage LDO_3V3 = 3.3 V 0.2 V
(1) DEBUG_CTL1/2 do not have an internal pull-down resistance path.

6.20 I2C Slave Requirements and Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDA and SCL COMMON CHARACTERISTICS
ILEAK Input leakage current Voltage on Pin = LDO_3V3 -3 3 μA
VOL SDA output low voltage IOL = 3 mA, LDO_3V3 = 3.3 V 0.4 V
IOL = 3 mA, VDDIO = 1.8 V 0.36
IOL SDA max output low current VOL = 0.4 V 3 mA
VOL = 0.6 V 6
VIL Input low signal LDO_3V3 = 3.3 V 0.99 V
VDDIO = 1.8 V 0.54
VIH Input high signal LDO_3V3 = 3.3 V 2.31 V
VDDIO = 1.8 V 1.26
VHYS Input Hysteresis LDO_3V3 = 3.3 V 0.17 V
VDDIO = 1.8 V 0.09
TSP I2C pulse width suppressed 50 ns
CI Pin Capacitance 10 pF
SDA and SCL STANDARD MODE CHARACTERISTICS
FSCL I2C clock frequency 0 100 kHz
THIGH I2C clock high time 4 μs
TLOW I2C clock low time 4.7 μs
TSUDAT I2C serial data setup time 250 ns
THDDAT I2C serial data hold time 0 ns
TVDDAT I2C Valid data time SCL low to SDA output valid 3.4 μs
TVDACK I2C Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.4 μs
TOCF I2C output fall time 10 pF to 400 pF bus 250 ns
TBUF I2C bus free time between stop and start 4.7 μs
TSTS I2C start or repeated Start condition setup time 4.7 μs
TSTH I2C Start or repeated Start condition hold time 4 μs
TSPS I2C Stop condition setup time 4 μs
SDA and SCL FAST MODE CHARACTERISTICS
FSCL I2C clock frequency 0 400 kHz
THIGH I2C clock high time 0.6 μs
TLOW I2C clock low time 1.3 μs
TSUDAT I2C serial data setup time 100 ns
THDDAT I2C serial data hold time 0 ns
TVDDAT I2C Valid data time SCL low to SDA output valid 0.9 μs
TVDACK I2C Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 0.9 μs
TOCF I2C output fall time 10 pF to 400 pF bus, VDD = 3.3 V 12 250 ns
10 pF to 400 pF bus, VDD = 1.8 V 6.5 250
TBUF I2C bus free time between stop and start 1.3 μs
TSTS I2Cstart or repeated Start condition setup time 0.6 μs
TSTH I2C Start or repeated Start condition hold time 0.6 μs
TSPS I2C Stop condition setup time 0.6 μs

6.21 SPI Master Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FSPI Frequency of SPI_CLK 11.82 12 12.18 MHz
TPER Period of SPI_CLK (1/F_SPI) 82.1 83.33 84.6 ns
TWHI SPI_CLK High Width 30 ns
TWLO SPI_CLK Low Width 30 ns
TDACT SPI_SZZ falling to SPI_CLK rising delay time 30 50 ns
TDINACT SPI_CLK falling to SPI_SSZ rising delay time 160 180 ns
TDMOSI SPI_CLK falling to SPI_MOSI Valid delay time –5 5 ns
TSUMISO SPI_MISO valid to SPI_CLK falling setup time 21 ns
THDMSIO SPI_CLK falling to SPI_MISO invalid hold time 0 ns
TRSPI SPI_SSZ/CLK/MOSI rise time 10% to 90%, CL = 5 pF to 50 pF, LDO_3V3 = 3.3 V 0.1 8 ns
TFSPI SPI_SSZ/CLK/MOSI fall time 90% to 10%, CL = 5 pF to 50 pF, LDO_3V3 = 3.3 V 0.1 8 ns

6.22 Single-Wire Debugger (SWD) Timing Requirements

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FSWD Frequency of SWD_CLK 10 MHz
TPER Period of SWD_CLK (1/FSWD) 100 ns
TWHI SWD_CLK High Width 35 ns
TWLO SWD_CLK Low Width 35 ns
TDOUT SWD_CLK rising to SWD_DATA valid delay time 2 25 ns
TSUIN SWD_DATA valid to SWD_CLK rising setup time 9 ns
THDIN SWD_DATA hold time from SWD_CLK rising 3 ns
TRSWD SWD Output rise time 10% to 90%, CL = 5 pF to 50 pF, LDO_3V3 = 3.3 V 0.1 8 ns
TFSWD SWD Output fall time 90% to 10%, CL = 5 pF to 50 pF, LDO_3V3 = 3.3 V 0.1 8 ns

6.23 BUSPOWERZ Configuration Requirements

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBPZ_DIS1 BUSPOWERZ Voltage range 1 for disabling system power from VBUS 0.8 V
VBPZ_HV BUSPOWERZ Voltage for receiving VBUS Power through the PP_HV path 0.8 2.4 V
VBPZ_DIS2 BUSPOWERZ Voltage range 2 for disabling system power from VBUS 2.4 V

6.24 HPD Timing Requirements and Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DP SOURCE SIDE (HPD TX)
T_IRQ_MIN HPD IRQ minimum assert time 675 750 825 μs
T_3MS_MIN HPD Assert 3 ms minimum time 3 3.33 3.67 ms
DP SINK SIDE (HPD RX)
T_HPD_HDB HPD high de-bounce time HPD_HDB_SEL = 0 300 375 450 μs
HPD_HDB_SEL = 1 100 111 122 ms
T_HPD_LDB HPD low de-bounce time 300 375 450 μs
T_HPD_IRQ HPD IRQ limit time 1.35 1.5 1.65 ms

6.25 Thermal Shutdown Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSD_MAIN Thermal shutdown temperature of the main thermal shutdown Temperature rising 145  160 175 °C
TSDH_MAIN Thermal shutdown hysteresis of the main thermal shutdown Temperature falling 20 °C
TSD_PWR Thermal shutdown temperature of the power path block Temperature rising 135 150 165 °C
TSDH_PWR Thermal shutdown hysteresis of the power path block Temperature falling 37 °C
TSD_DG Programmable thermal shutdown detection de-glitch time 0.1 ms

6.26 Oscillator Requirements and Characteristics

Recommended operating conditions; TA = –10°C to +85°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FOSC_48M 48-MHz oscillator 47.28 48 48.72 MHz
FOSC_100K 100-kHz oscillator 95 100 105 kHz
RR_OSC External oscillator set resistance (0.2%) 14.985 15 15.015

6.27 Typical Characteristics

TPS65986 D001_SLVSD02_TPS65982.gif
Figure 1. PP_5V0 Switch On-Resistance vs Temperature
TPS65986 D003_SLVSD02_TPS65982.gif
A.
Figure 3. PP_CABLE Switch On-Resistance vs Temperature
TPS65986 D002_SLVSD02_TPS65982.gif
Figure 2. PP_HV Switch On-Resistance vs Temperature